Intel IXP42X User Manual
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006
DM
Order Number: 252480-006US
465
High-Speed Serial Interfaces—Intel
®
IXP42X product line and IXC1100 control plane
processors
illustrates that 4 E1 streams can be byte interleaved. The frame pulse occurs
at the first byte of the first E1 stream. No unassigned timeslots are necessary here as
the E1 frames can completely fill all the timeslots available.
When T1 frames are placed on this backplane bus, then unassigned timeslots are
required as a T1 frame is 24 timeslots wide unlike E1, which is 32 timeslots wide.
Byte interleaving involves disregarding four in every sixteen timeslots (as shown in
). The first 4 timeslots are unassigned except for the framing pulse, the
following 4 bytes are byte 0 of each T1 frame, the next 4 are byte 1 of each T1 frame
and the next 4 bytes are byte 2 of each T1 frame, the following 4 bytes are again
unassigned. Unassigned timeslots are dictated by the look up tables.
Frame interleaving T1 frames onto this backplane bus would be to process the first T1
frame in its entirety starting with the first timeslot and finishing on the 24th timeslot,
the frame bit/pulse is located on the last bit of the 32nd timeslot.
Figure 94.
MVIP, Byte Interleaving Four E1 Streams on a 8.192-Mbps Backplane Bus
B4253-02
0
0
1
2
3
4
5
6
7
0
1 2
3
4
5
6
7
6
5
4
3
2
1
0
7
6
7
0a 0b 0c 0d
2a 2b 2c 2d 3a 3b 3c 3d 4a 4b 4c 4d 5a 5b 5c 5d 6a 6b 6c 6d 7a 7b 7c 7d 8a8b 8c 8d
Timeslots
Bits
31d
9a
8.192
MHz clock
Frame pulse
1
2 3
4
5
6 7
1d
1c
1b
1a
Figure 95.
MVIP, Byte Interleaving Four T1 Streams on a 8.192-Mbps Backplane Bus
0
x
x
x
x
x
x
x
x
0
1
2
3
4
5
7
6
5
4
3
2
1
0
7
6
6
Xa
Xb
Xc
Xd
0a
0b
0c
0d
1a
1b
1c
1d
2a
2b
2c
2d
Xa
Xb
Xc
Xd
3a
3b
3c
3d
4a
4b
4c
4d
5a
5b
5c
5d
Timeslots
Bits
31d
Xa
8.192
MHz clock
Frame pulse
x
x
x
x
x
x
x
Unused Bytes
Frame pulse plus 7 unused bits
7