Intel 253668-032US User Manual
4-8 Vol. 3
PAGING
and bits 20:12 identify a fourth. Again, the last identifies the page frame. (See
Figure 4-8 for an illustration.)
Figure 4-8 for an illustration.)
The translation process in each of the examples above completes by identifying a
page frame. However, the paging structures may be configured so that translation
terminates before doing so. This occurs if process encounters a paging-structure
entry that is marked “not present” (because its P flag — bit 0 — is clear) or in which
a reserved bit is set. In this case, there is no translation for the linear address; an
access to that address causes a page-fault exception (see Section 4.7).
In the examples above, a paging-structure entry maps a page with 4-KByte page
frame when only 12 bits remain in the linear address; entries identified earlier always
reference other paging structures. That may not apply in other cases. The following
items identify when an entry maps a page and when it references another paging
structure:
page frame. However, the paging structures may be configured so that translation
terminates before doing so. This occurs if process encounters a paging-structure
entry that is marked “not present” (because its P flag — bit 0 — is clear) or in which
a reserved bit is set. In this case, there is no translation for the linear address; an
access to that address causes a page-fault exception (see Section 4.7).
In the examples above, a paging-structure entry maps a page with 4-KByte page
frame when only 12 bits remain in the linear address; entries identified earlier always
reference other paging structures. That may not apply in other cases. The following
items identify when an entry maps a page and when it references another paging
structure:
•
If more than 12 bits remain in the linear address, bit 7 (PS — page size) of the
current paging-structure entry is consulted. If the bit is 0, the entry references
another paging structure; if the bit is 1, the entry maps a page.
current paging-structure entry is consulted. If the bit is 0, the entry references
another paging structure; if the bit is 1, the entry maps a page.
•
If only 12 bits remain in the linear address, the current paging-structure entry
always maps a page (bit 7 is used for other purposes).
always maps a page (bit 7 is used for other purposes).
If a paging-structure entry maps a page when more than 12 bits remain in the linear
address, the entry identifies a page frame larger than 4 KBytes. For example, 32-bit
paging uses the upper 10 bits of a linear address to locate the first paging-structure
entry; 22 bits remain. If that entry maps a page, the page frame is 2
address, the entry identifies a page frame larger than 4 KBytes. For example, 32-bit
paging uses the upper 10 bits of a linear address to locate the first paging-structure
entry; 22 bits remain. If that entry maps a page, the page frame is 2
22
Bytes = 4
MBytes. 32-bit paging supports 4-MByte pages if CR4.PSE = 1. PAE paging and
IA-32e paging support 2-MByte pages (regardless of the value of CR4.PSE).
Paging structures are given different names based their uses in the translation
process. Table 4-2 gives the names of the different paging structures. It also
provides, for each structure, the source of the physical address used to locate it (CR3
or a different paging-structure entry); the bits in the linear address used to select an
entry from the structure; and details of about whether and how such an entry can
map a page.
IA-32e paging support 2-MByte pages (regardless of the value of CR4.PSE).
Paging structures are given different names based their uses in the translation
process. Table 4-2 gives the names of the different paging structures. It also
provides, for each structure, the source of the physical address used to locate it (CR3
or a different paging-structure entry); the bits in the linear address used to select an
entry from the structure; and details of about whether and how such an entry can
map a page.
4.3 32-BIT
PAGING
A logical processor uses 32-bit paging if CR0.PG = 1 and CR4.PAE = 0. 32-bit paging
translates 32-bit linear addresses to 40-bit physical addresses.
translates 32-bit linear addresses to 40-bit physical addresses.
1
Although 40 bits
1. Bits in the range 39:32 are 0 in any physical address used by 32-bit paging except those used to
map 4-MByte pages. If the processor does not support the PSE-36 mechanism, this is true also
for physical addresses used to map 4-MByte pages. If the processor does support the PSE-36
mechanism and MAXPHYADDR < 40, bits in the range 39:MAXPHYADDR are 0 in any physical
address used to map a 4-MByte page. (The corresponding bits are reserved in PDEs.) See Section
4.1.4 for how to determine MAXPHYADDR and whether the PSE-36 mechanism is supported.