Intel 253668-032US User Manual
Vol. 3 4-47
PAGING
In addition to the instructions identified above, page faults invalidate entries in the
TLBs and paging-structure caches. In particular, a page-fault exception resulting
from an attempt to use a linear address will invalidate any PML4-cache, PDPTE-
cache, and PDE-cache entries that would be used for that linear address as well as
any TLB entry for that address's page number.
TLBs and paging-structure caches. In particular, a page-fault exception resulting
from an attempt to use a linear address will invalidate any PML4-cache, PDPTE-
cache, and PDE-cache entries that would be used for that linear address as well as
any TLB entry for that address's page number.
1
These invalidations ensure that the
page-fault exception will not recur (if the faulting instruction is re-executed) if it
would not be caused by the contents of the paging structures in memory (and if,
therefore, it resulted from cached entries that were not invalidated after the paging
structures were modified in memory).
As noted in Section 4.10.1, some processors may choose to cache multiple smaller-
page TLB entries for a translation specified by the paging structures to use a page
larger than 4 KBytes. There is no way for software to be aware that multiple transla-
tions for smaller pages have been used for a large page. The INVLPG instruction and
page faults provide the same assurances that they provide when a single TLB entry is
used: they invalidate all TLB entries corresponding to the translation specified by the
paging structures.
would not be caused by the contents of the paging structures in memory (and if,
therefore, it resulted from cached entries that were not invalidated after the paging
structures were modified in memory).
As noted in Section 4.10.1, some processors may choose to cache multiple smaller-
page TLB entries for a translation specified by the paging structures to use a page
larger than 4 KBytes. There is no way for software to be aware that multiple transla-
tions for smaller pages have been used for a large page. The INVLPG instruction and
page faults provide the same assurances that they provide when a single TLB entry is
used: they invalidate all TLB entries corresponding to the translation specified by the
paging structures.
4.10.3.2 Recommended Invalidation
The following items provide some recommendations regarding when software should
perform invalidations:
perform invalidations:
•
If software modifies a paging-structure entry that identifies the final page frame
for a page number (either a PTE or a PDE in which the PS flag is 1), it should
execute INVLPG for any linear address with a page number whose translation
uses that PTE.
for a page number (either a PTE or a PDE in which the PS flag is 1), it should
execute INVLPG for any linear address with a page number whose translation
uses that PTE.
2
(If the paging-structure entry may be used in the translation of
different page numbers — see Section 4.10.2.3 — software should execute
INVLPG for linear addresses with each of those page numbers; alternatively, it
could use MOV to CR3 or MOV to CR4.)
INVLPG for linear addresses with each of those page numbers; alternatively, it
could use MOV to CR3 or MOV to CR4.)
•
If software modifies a paging-structure entry that references another paging
structure, it may use one of the following approaches depending upon the types
and number of translations controlled by the modified entry:
— Execute INVLPG for linear addresses with each of the page numbers with
structure, it may use one of the following approaches depending upon the types
and number of translations controlled by the modified entry:
— Execute INVLPG for linear addresses with each of the page numbers with
translations that would use the entry. However, if no page numbers that
would use the entry have translations (e.g., because the P flags are 0 in all
entries in the paging structure referenced by the modified entry), it remains
necessary to execute INVLPG at least once.
would use the entry have translations (e.g., because the P flags are 0 in all
entries in the paging structure referenced by the modified entry), it remains
necessary to execute INVLPG at least once.
— Execute MOV to CR3 if the modified entry controls no global pages.
— Execute MOV to CR4 to modify CR4.PGE.
— Execute MOV to CR4 to modify CR4.PGE.
1. Unlike INVLPG, page faults need not invalidate all entries in the paging-structure caches, only
those that would be used to translate the faulting linear address.
2. One execution of INVLPG is sufficient even for a page with size greater than 4 KBytes.