Intel 253668-032US User Manual
6-26 Vol. 3
INTERRUPT AND EXCEPTION HANDLING
In summary, a stack switch in IA-32e mode works like the legacy stack switch,
except that a new SS selector is not loaded from the TSS. Instead, the new SS is
forced to NULL.
except that a new SS selector is not loaded from the TSS. Instead, the new SS is
forced to NULL.
6.14.5
Interrupt Stack Table
In IA-32e mode, a new interrupt stack table (IST) mechanism is available as an alter-
native to the modified legacy stack-switching mechanism described above. This
mechanism unconditionally switches stacks when it is enabled. It can be enabled on
an individual interrupt-vector basis using a field in the IDT entry. This means that
some interrupt vectors can use the modified legacy mechanism and others can use
the IST mechanism.
The IST mechanism is only available in IA-32e mode. It is part of the 64-bit mode
TSS. The motivation for the IST mechanism is to provide a method for specific inter-
rupts (such as NMI, double-fault, and machine-check) to always execute on a known
good stack. In legacy mode, interrupts can use the task-switch mechanism to set up
a known-good stack by accessing the interrupt service routine through a task gate
located in the IDT. However, the legacy task-switch mechanism is not supported in
IA-32e mode.
The IST mechanism provides up to seven IST pointers in the TSS. The pointers are
referenced by an interrupt-gate descriptor in the interrupt-descriptor table (IDT);
see Figure 6-7. The gate descriptor contains a 3-bit IST index field that provides an
offset into the IST section of the TSS. Using the IST mechanism, the processor loads
the value pointed by an IST pointer into the RSP.
When an interrupt occurs, the new SS selector is forced to NULL and the SS selector’s
RPL field is set to the new CPL. The old SS, RSP, RFLAGS, CS, and RIP are pushed
onto the new stack. Interrupt processing then proceeds as normal. If the IST index is
zero, the modified legacy stack-switching mechanism described above is used.
native to the modified legacy stack-switching mechanism described above. This
mechanism unconditionally switches stacks when it is enabled. It can be enabled on
an individual interrupt-vector basis using a field in the IDT entry. This means that
some interrupt vectors can use the modified legacy mechanism and others can use
the IST mechanism.
The IST mechanism is only available in IA-32e mode. It is part of the 64-bit mode
TSS. The motivation for the IST mechanism is to provide a method for specific inter-
rupts (such as NMI, double-fault, and machine-check) to always execute on a known
good stack. In legacy mode, interrupts can use the task-switch mechanism to set up
a known-good stack by accessing the interrupt service routine through a task gate
located in the IDT. However, the legacy task-switch mechanism is not supported in
IA-32e mode.
The IST mechanism provides up to seven IST pointers in the TSS. The pointers are
referenced by an interrupt-gate descriptor in the interrupt-descriptor table (IDT);
see Figure 6-7. The gate descriptor contains a 3-bit IST index field that provides an
offset into the IST section of the TSS. Using the IST mechanism, the processor loads
the value pointed by an IST pointer into the RSP.
When an interrupt occurs, the new SS selector is forced to NULL and the SS selector’s
RPL field is set to the new CPL. The old SS, RSP, RFLAGS, CS, and RIP are pushed
onto the new stack. Interrupt processing then proceeds as normal. If the IST index is
zero, the modified legacy stack-switching mechanism described above is used.
Figure 6-8. IA-32e Mode Stack Usage After Privilege Level Change
CS
Error Code
RFLAGS
RIP
SS
RSP
Stack Usage with
Privilege-Level Change
Handler’s Stack
Stack Pointer After
Transfer to Handler
CS
Error Code
EFLAGS
EIP
SS
ESP
Handler’s Stack
Legacy Mode
IA-32e Mode
0
+4
+8
+12
+16
+20
0
+8
+16
+24
+32
+40