Intel 253668-032US User Manual
6-62 Vol. 3
INTERRUPT AND EXCEPTION HANDLING
Interrupt 18—Machine-Check Exception (#MC)
Exception Class
Abort.
Description
Indicates that the processor detected an internal machine error or a bus error, or that
an external agent detected a bus error. The machine-check exception is model-
specific, available on the Pentium and later generations of processors. The imple-
mentation of the machine-check exception is different between different processor
families, and these implementations may not be compatible with future Intel 64 or
IA-32 processors. (Use the CPUID instruction to determine whether this feature is
present.)
Bus errors detected by external agents are signaled to the processor on dedicated
pins: the BINIT# and MCERR# pins on the Pentium 4, Intel Xeon, and P6 family
processors and the BUSCHK# pin on the Pentium processor. When one of these pins
is enabled, asserting the pin causes error information to be loaded into machine-
check registers and a machine-check exception is generated.
The machine-check exception and machine-check architecture are discussed in detail
in Chapter 15, “Machine-Check Architecture.” Also, see the data books for the indi-
vidual processors for processor-specific hardware information.
an external agent detected a bus error. The machine-check exception is model-
specific, available on the Pentium and later generations of processors. The imple-
mentation of the machine-check exception is different between different processor
families, and these implementations may not be compatible with future Intel 64 or
IA-32 processors. (Use the CPUID instruction to determine whether this feature is
present.)
Bus errors detected by external agents are signaled to the processor on dedicated
pins: the BINIT# and MCERR# pins on the Pentium 4, Intel Xeon, and P6 family
processors and the BUSCHK# pin on the Pentium processor. When one of these pins
is enabled, asserting the pin causes error information to be loaded into machine-
check registers and a machine-check exception is generated.
The machine-check exception and machine-check architecture are discussed in detail
in Chapter 15, “Machine-Check Architecture.” Also, see the data books for the indi-
vidual processors for processor-specific hardware information.
Exception Error Code
None. Error information is provide by machine-check MSRs.
Saved Instruction Pointer
For the Pentium 4 and Intel Xeon processors, the saved contents of extended
machine-check state registers are directly associated with the error that caused the
machine-check exception to be generated (see Section 15.3.1.2,
“IA32_MCG_STATUS MSR,” and Section 15.3.2.6, “IA32_MCG Extended Machine
Check State MSRs”).
For the P6 family processors, if the EIPV flag in the MCG_STATUS MSR is set, the
saved contents of CS and EIP registers are directly associated with the error that
caused the machine-check exception to be generated; if the flag is clear, the saved
instruction pointer may not be associated with the error (see Section 15.3.1.2,
“IA32_MCG_STATUS MSR”).
For the Pentium processor, contents of the CS and EIP registers may not be associ-
ated with the error.
machine-check state registers are directly associated with the error that caused the
machine-check exception to be generated (see Section 15.3.1.2,
“IA32_MCG_STATUS MSR,” and Section 15.3.2.6, “IA32_MCG Extended Machine
Check State MSRs”).
For the P6 family processors, if the EIPV flag in the MCG_STATUS MSR is set, the
saved contents of CS and EIP registers are directly associated with the error that
caused the machine-check exception to be generated; if the flag is clear, the saved
instruction pointer may not be associated with the error (see Section 15.3.1.2,
“IA32_MCG_STATUS MSR”).
For the Pentium processor, contents of the CS and EIP registers may not be associ-
ated with the error.
Program State Change
The machine-check mechanism is enabled by setting the MCE flag in control register
CR4.
CR4.