Intel 253668-032US User Manual
Vol. 3 7-1
CHAPTER 7
TASK MANAGEMENT
This chapter describes the IA-32 architecture’s task management facilities. These
facilities are only available when the processor is running in protected mode.
This chapter focuses on 32-bit tasks and the 32-bit TSS structure. For information on
16-bit tasks and the 16-bit TSS structure, see Section 7.6, “16-Bit Task-State
Segment (TSS).” For information specific to task management in 64-bit mode, see
Section 7.7, “Task Management in 64-bit Mode.”
facilities are only available when the processor is running in protected mode.
This chapter focuses on 32-bit tasks and the 32-bit TSS structure. For information on
16-bit tasks and the 16-bit TSS structure, see Section 7.6, “16-Bit Task-State
Segment (TSS).” For information specific to task management in 64-bit mode, see
Section 7.7, “Task Management in 64-bit Mode.”
7.1
TASK MANAGEMENT OVERVIEW
A task is a unit of work that a processor can dispatch, execute, and suspend. It can
be used to execute a program, a task or process, an operating-system service utility,
an interrupt or exception handler, or a kernel or executive utility.
The IA-32 architecture provides a mechanism for saving the state of a task, for
dispatching tasks for execution, and for switching from one task to another. When
operating in protected mode, all processor execution takes place from within a task.
Even simple systems must define at least one task. More complex systems can use
the processor’s task management facilities to support multitasking applications.
be used to execute a program, a task or process, an operating-system service utility,
an interrupt or exception handler, or a kernel or executive utility.
The IA-32 architecture provides a mechanism for saving the state of a task, for
dispatching tasks for execution, and for switching from one task to another. When
operating in protected mode, all processor execution takes place from within a task.
Even simple systems must define at least one task. More complex systems can use
the processor’s task management facilities to support multitasking applications.
7.1.1 Task
Structure
A task is made up of two parts: a task execution space and a task-state segment
(TSS). The task execution space consists of a code segment, a stack segment, and
one or more data segments (see Figure 7-1). If an operating system or executive
uses the processor’s privilege-level protection mechanism, the task execution space
also provides a separate stack for each privilege level.
The TSS specifies the segments that make up the task execution space and provides
a storage place for task state information. In multitasking systems, the TSS also
provides a mechanism for linking tasks.
A task is identified by the segment selector for its TSS. When a task is loaded into the
processor for execution, the segment selector, base address, limit, and segment
descriptor attributes for the TSS are loaded into the task register (see Section 2.4.4,
“Task Register (TR)”).
If paging is implemented for the task, the base address of the page directory used by
the task is loaded into control register CR3.
(TSS). The task execution space consists of a code segment, a stack segment, and
one or more data segments (see Figure 7-1). If an operating system or executive
uses the processor’s privilege-level protection mechanism, the task execution space
also provides a separate stack for each privilege level.
The TSS specifies the segments that make up the task execution space and provides
a storage place for task state information. In multitasking systems, the TSS also
provides a mechanism for linking tasks.
A task is identified by the segment selector for its TSS. When a task is loaded into the
processor for execution, the segment selector, base address, limit, and segment
descriptor attributes for the TSS are loaded into the task register (see Section 2.4.4,
“Task Register (TR)”).
If paging is implemented for the task, the base address of the page directory used by
the task is loaded into control register CR3.