Intel 253668-032US User Manual
Vol. 3 7-23
TASK MANAGEMENT
Although hardware task-switching is not supported in 64-bit mode, a 64-bit task
state segment (TSS) must exist. Figure 7-11 shows the format of a 64-bit TSS. The
TSS holds information important to 64-bit mode and that is not directly related to the
task-switch mechanism. This information includes:
state segment (TSS) must exist. Figure 7-11 shows the format of a 64-bit TSS. The
TSS holds information important to 64-bit mode and that is not directly related to the
task-switch mechanism. This information includes:
•
RSPn — The full 64-bit canonical forms of the stack pointers (RSP) for privilege
levels 0-2.
levels 0-2.
•
ISTn — The full 64-bit canonical forms of the interrupt stack table (IST) pointers.
•
I/O map base address — The 16-bit offset to the I/O permission bit map from
the 64-bit TSS base.
the 64-bit TSS base.
The operating system must create at least one 64-bit TSS after activating IA-32e
mode. It must execute the LTR instruction (in 64-bit mode) to load the TR register
with a pointer to the 64-bit TSS responsible for both 64-bit-mode programs and
compatibility-mode programs.
mode. It must execute the LTR instruction (in 64-bit mode) to load the TR register
with a pointer to the 64-bit TSS responsible for both 64-bit-mode programs and
compatibility-mode programs.