Intel 253668-032US User Manual
8-12 Vol. 3
MULTIPLE-PROCESSOR MANAGEMENT
Section 8.2.3.2 through Section 8.2.3.7 give examples using the MOV instruction.
The principles that underlie these examples apply to load and store accesses in
general and to other instructions that load from or store to memory. Section 8.2.3.8
and Section 8.2.3.9 give examples using the XCHG instruction. The principles that
underlie these examples apply to other locked read-modify-write instructions.
This section uses the term “processor” is to refer to a logical processor. The examples
are written using Intel-64 assembly-language syntax and use the following nota-
tional conventions:
The principles that underlie these examples apply to load and store accesses in
general and to other instructions that load from or store to memory. Section 8.2.3.8
and Section 8.2.3.9 give examples using the XCHG instruction. The principles that
underlie these examples apply to other locked read-modify-write instructions.
This section uses the term “processor” is to refer to a logical processor. The examples
are written using Intel-64 assembly-language syntax and use the following nota-
tional conventions:
•
Arguments beginning with an “r”, such as r1 or r2 refer to registers (e.g., EAX)
visible only to the processor being considered.
visible only to the processor being considered.
•
Memory locations are denoted with x, y, z.
•
Stores are written as mov [ _x], val, which implies that val is being stored into
the memory location x.
the memory location x.
•
Loads are written as mov r, [ _x], which implies that the contents of the memory
location x are being loaded into the register r.
location x are being loaded into the register r.
As noted earlier, the examples refer only to software visible behavior. When the
succeeding sections make statement such as “the two stores are reordered,” the
implication is only that “the two stores appear to be reordered from the point of view
of software.”
succeeding sections make statement such as “the two stores are reordered,” the
implication is only that “the two stores appear to be reordered from the point of view
of software.”
8.2.3.2
Neither Loads Nor Stores Are Reordered with Like Operations
The Intel-64 memory-ordering model allows neither loads nor stores to be reordered
with the same kind of operation. That is, it ensures that loads are seen in program
order and that stores are seen in program order. This is illustrated by the following
example:
with the same kind of operation. That is, it ensures that loads are seen in program
order and that stores are seen in program order. This is illustrated by the following
example:
The disallowed return values could be exhibited only if processor 0’s two stores are
reordered (with the two loads occurring between them) or if processor 1’s two loads
are reordered (with the two stores occurring between them).
reordered (with the two loads occurring between them) or if processor 1’s two loads
are reordered (with the two stores occurring between them).
If r1 == 1, the store to y occurs before the load from y. Because the Intel-64
memory-ordering model does not allow stores to be reordered, the earlier store to x
occurs before the load from y. Because the Intel-64 memory-ordering model does
not allow loads to be reordered, the store to x also occurs before the later load from
x. This r2 == 1.
memory-ordering model does not allow stores to be reordered, the earlier store to x
occurs before the load from y. Because the Intel-64 memory-ordering model does
not allow loads to be reordered, the store to x also occurs before the later load from
x. This r2 == 1.
Example 8-1. Stores Are Not Reordered with Other Stores
Processor 0
Processor 1
mov [ _x], 1
mov r1, [ _y]
mov [ _y], 1
mov r2, [ _x]
Initially x == y == 0
r1 == 1 and r2 == 0 is not allowed
r1 == 1 and r2 == 0 is not allowed