Intel 253668-032US User Manual
8-26 Vol. 3
MULTIPLE-PROCESSOR MANAGEMENT
execution is not deterministically serialized when a branch instruction is
executed.
executed.
8.4
MULTIPLE-PROCESSOR (MP) INITIALIZATION
The IA-32 architecture (beginning with the P6 family processors) defines a multiple-
processor (MP) initialization protocol called the Multiprocessor Specification Version
1.4. This specification defines the boot protocol to be used by IA-32 processors in
multiple-processor systems. (Here, multiple processors is defined as two or more
processors.) The MP initialization protocol has the following important features:
processor (MP) initialization protocol called the Multiprocessor Specification Version
1.4. This specification defines the boot protocol to be used by IA-32 processors in
multiple-processor systems. (Here, multiple processors is defined as two or more
processors.) The MP initialization protocol has the following important features:
•
It supports controlled booting of multiple processors without requiring dedicated
system hardware.
system hardware.
•
It allows hardware to initiate the booting of a system without the need for a
dedicated signal or a predefined boot processor.
dedicated signal or a predefined boot processor.
•
It allows all IA-32 processors to be booted in the same manner, including those
supporting Intel Hyper-Threading Technology.
supporting Intel Hyper-Threading Technology.
•
The MP initialization protocol also applies to MP systems using Intel 64
processors.
processors.
The mechanism for carrying out the MP initialization protocol differs depending on
the IA-32 processor family, as follows:
the IA-32 processor family, as follows:
•
For P6 family processors — The selection of the BSP and APs (see Section
8.4.1, “BSP and AP Processors”) is handled through arbitration on the APIC bus,
using BIPI and FIPI messages. See Appendix C, “MP Initialization For P6 Family
Processors,” for a complete discussion of MP initialization for P6 family
processors.
8.4.1, “BSP and AP Processors”) is handled through arbitration on the APIC bus,
using BIPI and FIPI messages. See Appendix C, “MP Initialization For P6 Family
Processors,” for a complete discussion of MP initialization for P6 family
processors.
•
Intel Xeon processors with family, model, and stepping IDs up to F09H —
The selection of the BSP and APs (see Section 8.4.1, “BSP and AP Processors”) is
handled through arbitration on the system bus, using BIPI and FIPI messages
(see Section 8.4.3, “MP Initialization Protocol Algorithm for
Intel Xeon Processors”).
The selection of the BSP and APs (see Section 8.4.1, “BSP and AP Processors”) is
handled through arbitration on the system bus, using BIPI and FIPI messages
(see Section 8.4.3, “MP Initialization Protocol Algorithm for
Intel Xeon Processors”).
•
Intel Xeon processors with family, model, and stepping IDs of F0AH and
beyond, 6E0H and beyond, 6F0H and beyond — The selection of the BSP and
APs is handled through a special system bus cycle, without using BIPI and FIPI
message arbitration (see Section 8.4.3, “MP Initialization Protocol Algorithm for
Intel Xeon Processors”).
beyond, 6E0H and beyond, 6F0H and beyond — The selection of the BSP and
APs is handled through a special system bus cycle, without using BIPI and FIPI
message arbitration (see Section 8.4.3, “MP Initialization Protocol Algorithm for
Intel Xeon Processors”).
The family, model, and stepping ID for a processor is given in the EAX register when
the CPUID instruction is executed with a value of 1 in the EAX register.
the CPUID instruction is executed with a value of 1 in the EAX register.