Intel 253668-032US User Manual
8-64 Vol. 3
MULTIPLE-PROCESSOR MANAGEMENT
}
if (i == CoreNum) {
if (i == CoreNum) {
//Did not match any bucket, start new bucket
CoreIDBucket[i] = PackageID[ProcessorNum] | CoreID[ProcessorNum];
CoreProcessorMask[i] = ProcessorMask;
CoreNum++;
CoreIDBucket[i] = PackageID[ProcessorNum] | CoreID[ProcessorNum];
CoreProcessorMask[i] = ProcessorMask;
CoreNum++;
}
}
// CoreNum has the number of cores started in the OS
// CoreProcessorMask[] array has the processor set of each core
// CoreNum has the number of cores started in the OS
// CoreProcessorMask[] array has the processor set of each core
Other processor relationships such as processor mask of sibling cores can be
computed from set operations of the PackageProcessorMask[] and CoreProcessor-
Mask[].
The algorithm shown above can be adapted to work with earlier generations of
single-core IA-32 processors that support Intel Hyper-Threading Technology and in
situations that the deterministic cache parameter leaf is not supported (provided
CPUID supports initial APIC ID). A reference code example is available (see Intel® 64
Architecture Processor Topology Enumeration).
computed from set operations of the PackageProcessorMask[] and CoreProcessor-
Mask[].
The algorithm shown above can be adapted to work with earlier generations of
single-core IA-32 processors that support Intel Hyper-Threading Technology and in
situations that the deterministic cache parameter leaf is not supported (provided
CPUID supports initial APIC ID). A reference code example is available (see Intel® 64
Architecture Processor Topology Enumeration).
8.10
MANAGEMENT OF IDLE AND BLOCKED CONDITIONS
When a logical processor in an MP system (including multi-core processor or proces-
sors supporting Intel Hyper-Threading Technology) is idle (no work to do) or blocked
(on a lock or semaphore), additional management of the core execution engine
resource can be accomplished by using the HLT (halt), PAUSE, or the
MONITOR/MWAIT instructions.
sors supporting Intel Hyper-Threading Technology) is idle (no work to do) or blocked
(on a lock or semaphore), additional management of the core execution engine
resource can be accomplished by using the HLT (halt), PAUSE, or the
MONITOR/MWAIT instructions.
8.10.1 HLT
Instruction
The HLT instruction stops the execution of the logical processor on which it is
executed and places it in a halted state until further notice (see the description of the
HLT instruction in Chapter 3 of the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A). When a logical processor is halted, active logical
processors continue to have full access to the shared resources within the physical
package. Here shared resources that were being used by the halted logical processor
become available to active logical processors, allowing them to execute at greater
efficiency. When the halted logical processor resumes execution, shared resources
are again shared among all active logical processors. (See Section 8.10.6.3, “Halt
Idle Logical Processors,” for more information about using the HLT instruction with
processors supporting Intel Hyper-Threading Technology.)
executed and places it in a halted state until further notice (see the description of the
HLT instruction in Chapter 3 of the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A). When a logical processor is halted, active logical
processors continue to have full access to the shared resources within the physical
package. Here shared resources that were being used by the halted logical processor
become available to active logical processors, allowing them to execute at greater
efficiency. When the halted logical processor resumes execution, shared resources
are again shared among all active logical processors. (See Section 8.10.6.3, “Halt
Idle Logical Processors,” for more information about using the HLT instruction with
processors supporting Intel Hyper-Threading Technology.)