Intel 253668-032US User Manual
8-72 Vol. 3
MULTIPLE-PROCESSOR MANAGEMENT
{
MONITOR WorkQueue // Setup of eax with WorkQueue LinearAddress,
// ECX, EDX = 0
IF (WorkQueue != 0) THEN {
STI
MWAIT
MWAIT
// EAX, ECX = 0
}
}
8.10.6.5 Guidelines for Scheduling Threads on Logical Processors Sharing
Execution Resources
Because the logical processors, the order in which threads are dispatched to logical
processors for execution can affect the overall efficiency of a system. The following
guidelines are recommended for scheduling threads for execution.
processors for execution can affect the overall efficiency of a system. The following
guidelines are recommended for scheduling threads for execution.
•
Dispatch threads to one logical processor per processor core before dispatching
threads to the other logical processor sharing execution resources in the same
processor core.
threads to the other logical processor sharing execution resources in the same
processor core.
•
In an MP system with two or more physical packages, distribute threads out over
all the physical processors, rather than concentrate them in one or two physical
processors.
all the physical processors, rather than concentrate them in one or two physical
processors.
•
Use processor affinity to assign a thread to a specific processor core or package,
depending on the cache-sharing topology. The practice increases the chance that
the processor’s caches will contain some of the thread’s code and data when it is
dispatched for execution after being suspended.
depending on the cache-sharing topology. The practice increases the chance that
the processor’s caches will contain some of the thread’s code and data when it is
dispatched for execution after being suspended.
8.10.6.6 Eliminate Execution-Based Timing Loops
Intel discourages the use of timing loops that depend on a processor’s execution
speed to measure time. There are several reasons:
speed to measure time. There are several reasons:
•
Timing loops cause problems when they are calibrated on a IA-32 processor
running at one clock speed and then executed on a processor running at another
clock speed.
running at one clock speed and then executed on a processor running at another
clock speed.
•
Routines for calibrating execution-based timing loops produce unpredictable
results when run on an IA-32 processor supporting Intel Hyper-Threading
Technology. This is due to the sharing of execution resources between the logical
processors within a physical package.
results when run on an IA-32 processor supporting Intel Hyper-Threading
Technology. This is due to the sharing of execution resources between the logical
processors within a physical package.
To avoid the problems described, timing loop routines must use a timing mechanism
for the loop that does not depend on the execution speed of the logical processors in
the system. The following sources are generally available:
for the loop that does not depend on the execution speed of the logical processors in
the system. The following sources are generally available:
•
A high resolution system timer (for example, an Intel 8254).