Intel 253668-032US User Manual
9-12 Vol. 3
PROCESSOR MANAGEMENT AND INITIALIZATION
modules into memory to support reliable operation of the processor in protected
mode. These data structures include the following:
mode. These data structures include the following:
•
A IDT.
•
A GDT.
•
A TSS.
•
(Optional) An LDT.
•
If paging is to be used, at least one page directory and one page table.
•
A code segment that contains the code to be executed when the processor
switches to protected mode.
switches to protected mode.
•
One or more code modules that contain the necessary interrupt and exception
handlers.
handlers.
Software initialization code must also initialize the following system registers before
the processor can be switched to protected mode:
the processor can be switched to protected mode:
•
The GDTR.
•
(Optional.) The IDTR. This register can also be initialized immediately after
switching to protected mode, prior to enabling interrupts.
switching to protected mode, prior to enabling interrupts.
•
Control registers CR1 through CR4.
•
(Pentium 4, Intel Xeon, and P6 family processors only.) The memory type range
registers (MTRRs).
registers (MTRRs).
With these data structures, code modules, and system registers initialized, the
processor can be switched to protected mode by loading control register CR0 with a
value that sets the PE flag (bit 0).
processor can be switched to protected mode by loading control register CR0 with a
value that sets the PE flag (bit 0).
9.8.1 Protected-Mode
System Data Structures
The contents of the protected-mode system data structures loaded into memory
during software initialization, depend largely on the type of memory management
the protected-mode operating-system or executive is going to support: flat, flat with
paging, segmented, or segmented with paging.
To implement a flat memory model without paging, software initialization code must
at a minimum load a GDT with one code and one data-segment descriptor. A null
descriptor in the first GDT entry is also required. The stack can be placed in a normal
read/write data segment, so no dedicated descriptor for the stack is required. A flat
memory model with paging also requires a page directory and at least one page table
(unless all pages are 4 MBytes in which case only a page directory is required). See
Section 9.8.3, “Initializing Paging.”
Before the GDT can be used, the base address and limit for the GDT must be loaded
into the GDTR register using an LGDT instruction.
A multi-segmented model may require additional segments for the operating system,
as well as segments and LDTs for each application program. LDTs require segment
during software initialization, depend largely on the type of memory management
the protected-mode operating-system or executive is going to support: flat, flat with
paging, segmented, or segmented with paging.
To implement a flat memory model without paging, software initialization code must
at a minimum load a GDT with one code and one data-segment descriptor. A null
descriptor in the first GDT entry is also required. The stack can be placed in a normal
read/write data segment, so no dedicated descriptor for the stack is required. A flat
memory model with paging also requires a page directory and at least one page table
(unless all pages are 4 MBytes in which case only a page directory is required). See
Section 9.8.3, “Initializing Paging.”
Before the GDT can be used, the base address and limit for the GDT must be loaded
into the GDTR register using an LGDT instruction.
A multi-segmented model may require additional segments for the operating system,
as well as segments and LDTs for each application program. LDTs require segment