Intel 253668-032US User Manual
Vol. 3 9-45
PROCESSOR MANAGEMENT AND INITIALIZATION
If (ChkSum == 00000000H)
Success
Else
Fail
9.11.6 Microcode
Update
Loader
This section describes an update loader used to load an update into a Pentium 4, Intel
Xeon, or P6 family processor. It also discusses the requirements placed on the BIOS
to ensure proper loading. The update loader described contains the minimal instruc-
tions needed to load an update. The specific instruction sequence that is required to
load an update is dependent upon the loader revision field contained within the
update header. This revision is expected to change infrequently (potentially, only
when new processor models are introduced).
Example 9-8 below represents the update loader with a loader revision of
00000001H. Note that the microcode update must be aligned on a 16-byte boundary
and the size of the microcode update must be 1-KByte granular.
Xeon, or P6 family processor. It also discusses the requirements placed on the BIOS
to ensure proper loading. The update loader described contains the minimal instruc-
tions needed to load an update. The specific instruction sequence that is required to
load an update is dependent upon the loader revision field contained within the
update header. This revision is expected to change infrequently (potentially, only
when new processor models are introduced).
Example 9-8 below represents the update loader with a loader revision of
00000001H. Note that the microcode update must be aligned on a 16-byte boundary
and the size of the microcode update must be 1-KByte granular.
Example 9-8. Assembly Code Example of Simple Microcode Update Loader
mov ecx,79h ; MSR to read in ECX
xor eax,eax ; clear EAX
xor ebx,ebx ; clear EBX
mov ax,cs ; Segment of microcode update
shl eax,4
mov bx,offset Update ; Offset of microcode update
add eax,ebx ; Linear Address of Update in EAX
add eax,48d ; Offset of the Update Data within the Update
xor edx,edx ; Zero in EDX
WRMSR ; microcode update trigger
The loader shown in Example 9-8 assumes that update is the address of a microcode
update (header and data) embedded within the code segment of the BIOS. It also
assumes that the processor is operating in real mode. The data may reside anywhere
in memory, aligned on a 16-byte boundary, that is accessible by the processor within
its current operating mode.
Before the BIOS executes the microcode update trigger (WRMSR) instruction, the
following must be true:
update (header and data) embedded within the code segment of the BIOS. It also
assumes that the processor is operating in real mode. The data may reside anywhere
in memory, aligned on a 16-byte boundary, that is accessible by the processor within
its current operating mode.
Before the BIOS executes the microcode update trigger (WRMSR) instruction, the
following must be true:
•
In 64-bit mode, EAX contains the lower 32-bits of the microcode update linear
address. In protected mode, EAX contains the full 32-bit linear address of the
microcode update.
address. In protected mode, EAX contains the full 32-bit linear address of the
microcode update.
•
In 64-bit mode, EDX contains the upper 32-bits of the microcode update linear
address. In protected mode, EDX equals zero.
address. In protected mode, EDX equals zero.