Intel 253668-032US User Manual
Vol. 3 10-5
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
The IPI mechanism is typically used in MP systems to send fixed interrupts (inter-
rupts for a specific vector number) and special-purpose interrupts to processors on
the system bus. For example, a local APIC can use an IPI to forward a fixed interrupt
to another processor for servicing. Special-purpose IPIs (including NMI, INIT, SMI
and SIPI IPIs) allow one or more processors on the system bus to perform system-
wide boot-up and control functions.
The following sections focus on the local APIC and its implementation in the
Pentium 4, Intel Xeon, and P6 family processors. In these sections, the terms “local
APIC” and “I/O APIC” refer to local and I/O APICs used with the P6 family processors
and to local and I/O xAPICs used with the Pentium 4 and Intel Xeon processors (see
Section 10.3, “the Intel
rupts for a specific vector number) and special-purpose interrupts to processors on
the system bus. For example, a local APIC can use an IPI to forward a fixed interrupt
to another processor for servicing. Special-purpose IPIs (including NMI, INIT, SMI
and SIPI IPIs) allow one or more processors on the system bus to perform system-
wide boot-up and control functions.
The following sections focus on the local APIC and its implementation in the
Pentium 4, Intel Xeon, and P6 family processors. In these sections, the terms “local
APIC” and “I/O APIC” refer to local and I/O APICs used with the P6 family processors
and to local and I/O xAPICs used with the Pentium 4 and Intel Xeon processors (see
Section 10.3, “the Intel
X2APIC”).
10.2
SYSTEM BUS VS. APIC BUS
For the P6 family and Pentium processors, the I/O APIC and local APICs communicate
through the 3-wire inter-APIC bus (see Figure 10-3). Local APICs also use the APIC
bus to send and receive IPIs. The APIC bus and its messages are invisible to software
and are not classed as architectural.
Beginning with the Pentium 4 and Intel Xeon processors, the I/O APIC and local
APICs (using the xAPIC architecture) communicate through the system bus (see
Figure 10-2). The I/O APIC sends interrupt requests to the processors on the system
bus through bridge hardware that is part of the Intel chip set. The bridge hardware
generates the interrupt messages that go to the local APICs. IPIs between local
APICs are transmitted directly on the system bus.
through the 3-wire inter-APIC bus (see Figure 10-3). Local APICs also use the APIC
bus to send and receive IPIs. The APIC bus and its messages are invisible to software
and are not classed as architectural.
Beginning with the Pentium 4 and Intel Xeon processors, the I/O APIC and local
APICs (using the xAPIC architecture) communicate through the system bus (see
Figure 10-2). The I/O APIC sends interrupt requests to the processors on the system
bus through bridge hardware that is part of the Intel chip set. The bridge hardware
generates the interrupt messages that go to the local APICs. IPIs between local
APICs are transmitted directly on the system bus.
10.3 THE
INTEL
®
82489DX EXTERNAL APIC,
THE APIC, THE XAPIC, AND THE X2APIC
The local APIC in the P6 family and Pentium processors is an architectural subset of
the Intel
the Intel
®
82489DX external APIC. See Section 19.27.1, “Software Visible Differ-
ences Between the Local APIC and the 82489DX.”
The APIC architecture used in the Pentium 4 and Intel Xeon processors (called the
xAPIC architecture) is an extension of the APIC architecture found in the P6 family
processors. The primary difference between the APIC and xAPIC architectures is that
with the xAPIC architecture, the local APICs and the I/O APIC communicate through
the system bus. With the APIC architecture, they communication through the APIC
bus (see Section 10.2, “System Bus Vs. APIC Bus”). Also, some APIC architectural
features have been extended and/or modified in the xAPIC architecture.
The x2APIC architecture is extended from the xAPIC architecture. Extensions to the
xAPIC architecture are intended primarily to increase processor addressability. The
x2APIC architecture provides backward compatibility to the xAPIC architecture and
The APIC architecture used in the Pentium 4 and Intel Xeon processors (called the
xAPIC architecture) is an extension of the APIC architecture found in the P6 family
processors. The primary difference between the APIC and xAPIC architectures is that
with the xAPIC architecture, the local APICs and the I/O APIC communicate through
the system bus. With the APIC architecture, they communication through the APIC
bus (see Section 10.2, “System Bus Vs. APIC Bus”). Also, some APIC architectural
features have been extended and/or modified in the xAPIC architecture.
The x2APIC architecture is extended from the xAPIC architecture. Extensions to the
xAPIC architecture are intended primarily to increase processor addressability. The
x2APIC architecture provides backward compatibility to the xAPIC architecture and