Intel 253668-032US User Manual
10-12 Vol. 3
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
•
APIC Global Enable flag, bit 11 ⎯ Enables or disables the local APIC (see
). This flag is available in
the Pentium 4, Intel Xeon, and P6 family processors. It is not guaranteed to be
available or available at the same location in future Intel 64 or IA-32 processors.
available or available at the same location in future Intel 64 or IA-32 processors.
•
APIC Base field, bits 12 through 35 ⎯ Specifies the base address of the APIC
registers. This 24-bit value is extended by 12 bits at the low end to form the base
address. This automatically aligns the address on a 4-KByte boundary. Following
a power-up or RESET, the field is set to FEE0 0000H.
address. This automatically aligns the address on a 4-KByte boundary. Following
a power-up or RESET, the field is set to FEE0 0000H.
•
Bits 0 through 7, bits 9 and 10, and bits MAXPHYADDR
1
through 63 in the
IA32_APIC_BASE MSR are reserved.
10.4.5
Relocating the Local APIC Registers
The Pentium 4, Intel Xeon, and P6 family processors permit the starting address of
the APIC registers to be relocated from FEE00000H to another physical address by
modifying the value in the 24-bit base address field of the IA32_APIC_BASE MSR.
This extension of the APIC architecture is provided to help resolve conflicts with
memory maps of existing systems and to allow individual processors in an MP system
to map their APIC registers to different locations in physical memory.
the APIC registers to be relocated from FEE00000H to another physical address by
modifying the value in the 24-bit base address field of the IA32_APIC_BASE MSR.
This extension of the APIC architecture is provided to help resolve conflicts with
memory maps of existing systems and to allow individual processors in an MP system
to map their APIC registers to different locations in physical memory.
10.4.6
Local APIC ID
At power up, system hardware assigns a unique APIC ID to each local APIC on the
system bus (for Pentium 4 and Intel Xeon processors) or on the APIC bus (for P6
family and Pentium processors). The hardware assigned APIC ID is based on system
topology and includes encoding for socket position and cluster information (see
system bus (for Pentium 4 and Intel Xeon processors) or on the APIC bus (for P6
family and Pentium processors). The hardware assigned APIC ID is based on system
topology and includes encoding for socket position and cluster information (see
).
In MP systems, the local APIC ID is also used as a processor ID by the BIOS and the
operating system. Some processors permit software to modify the APIC ID. However,
the ability of software to modify the APIC ID is processor model specific. Because of
operating system. Some processors permit software to modify the APIC ID. However,
the ability of software to modify the APIC ID is processor model specific. Because of
1. The MAXPHYADDR is 36 bits for processors that do not support CPUID leaf 80000008H, or indi-
cated by CPUID.80000008H:EAX[bits 7:0] for processors that support CPUID leaf 80000008H.
Figure 10-5. IA32_APIC_BASE MSR (APIC_BASE_MSR in P6 Family)
BSP—Processor is BSP
APIC global enable/disable
APIC Base—Base physical address
63
0
7
10
11
8
9
12
Reserved
MAXPHYADDR
APIC Base
Reserved