Intel 253668-032US User Manual
Vol. 3 10-17
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
, “x2APIC operating mode configurations” describe the possible combina-
tions of the enable bit (EN - bit 11) and the extended mode bit (EXTD - bit 10) in the
IA32_APIC_BASE MSR.
IA32_APIC_BASE MSR.
Once the local APIC has been switched to x2APIC mode (EN = 1, EXTD = 1),
switching back to xAPIC mode would require system software to disable the local
APIC unit. Specifically, attempting to write a value to the IA32_APIC_BASE MSR that
has (EN= 1, EXTD = 0) when the local APIC is enabled and in x2APIC mode will raise
a GP exception. Once bit 10 in IA32_APIC_BASE MSR is set, the only way to leave
x2APIC mode using IA32_APIC_BASE would require a WRMSR to set both bit 11 and
bit 10 to zero.
switching back to xAPIC mode would require system software to disable the local
APIC unit. Specifically, attempting to write a value to the IA32_APIC_BASE MSR that
has (EN= 1, EXTD = 0) when the local APIC is enabled and in x2APIC mode will raise
a GP exception. Once bit 10 in IA32_APIC_BASE MSR is set, the only way to leave
x2APIC mode using IA32_APIC_BASE would require a WRMSR to set both bit 11 and
bit 10 to zero.
provides a detailed state
diagram for the state transitions allowed for the local APIC.
10.5.1.1 Instructions to Access APIC Registers
In x2APIC mode, system software uses RDMSR and WRMSR to access the APIC regis-
ters. The MSR addresses for accessing the x2APIC registers are architecturally
defined and specified in
ters. The MSR addresses for accessing the x2APIC registers are architecturally
defined and specified in
. Executing
the RDMSR instruction with APIC register address specified in ECX returns the
content of bits 0 through 31 of the APIC registers in EAX. Bits 32 through 63 are
returned in register EDX - these bits are reserved if the APIC register being read is a
content of bits 0 through 31 of the APIC registers in EAX. Bits 32 through 63 are
returned in register EDX - these bits are reserved if the APIC register being read is a
Figure 10-8. IA32_APIC_BASE MSR Supporting x2APIC
Table 10-2. x2APIC Operating Mode Configurations
xAPIC global enable
(IA32_APIC_BASE[11])
x2APIC enable
(IA32_APIC_BASE[10]) Description
0
0
local APIC is disabled
0
1
Invalid
1
0
local APIC is enabled in xAPIC mode
1
1
local APIC is enabled in x2APIC mode
BSP—Processor is BSP
EN—xAPIC global enable/disable
APIC Base—Base physical address
63
0
7
10
11
8
9
12
Reserved
36 35
APIC Base
Reserved
EXTD—Enable x2APIC mode