Intel 253668-032US User Manual
10-28 Vol. 3
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
Support for the x2APIC architecture can be implemented in the local APIC unit. All
existing PCI/MSI capable devices and IOxAPIC unit should work with the x2APIC
extensions defined in this document. The x2APIC architecture also provides flexibility
to cope with the underlying fabrics that connect the PCI devices, IOxAPICs and Local
APIC units.
The extensions provided in this specification translate into modifications to:
existing PCI/MSI capable devices and IOxAPIC unit should work with the x2APIC
extensions defined in this document. The x2APIC architecture also provides flexibility
to cope with the underlying fabrics that connect the PCI devices, IOxAPICs and Local
APIC units.
The extensions provided in this specification translate into modifications to:
•
the local APIC unit,
•
the underlying fabrics connecting Message Signaled Interrupts (MSI) capable PCI
devices to local xAPICs,
devices to local xAPICs,
•
the underlying fabrics connecting the IOxAPICs to the local APIC units.
However no modifications are required to PCI or PCIe devices that support direct
interrupt delivery to the processors via Message Signaled Interrupts. Similarly no
modifications are required to the IOxAPIC. The routing of interrupts from these
devices in x2APIC mode leverages the interrupt remapping architecture specified in
the Intel
interrupt delivery to the processors via Message Signaled Interrupts. Similarly no
modifications are required to the IOxAPIC. The routing of interrupts from these
devices in x2APIC mode leverages the interrupt remapping architecture specified in
the Intel
®
Virtualization Technology for Directed I/O, Rev 1.2 specification.
Modifications to ACPI interfaces to support x2APIC are described in Appendix A,
“ACPI Extensions for x2APIC Support”, of the Intel
“ACPI Extensions for x2APIC Support”, of the Intel
®
64 Architecture x2APIC Specifi-
cation.
The default will be for the BIOS to pass the control to the OS with the local x2APICs
in xAPIC mode if all x2APIC IDs reported by CPUID.0BH:EDX are less than 255, and
in x2APIC mode if there are any logical processor reporting its x2APIC ID at 255 or
greater.
The default will be for the BIOS to pass the control to the OS with the local x2APICs
in xAPIC mode if all x2APIC IDs reported by CPUID.0BH:EDX are less than 255, and
in x2APIC mode if there are any logical processor reporting its x2APIC ID at 255 or
greater.
10.5.8
CPUID Extensions And Topology Enumeration
For Intel 64 and IA-32 processors that support x2APIC, a value of 1 reported by
CPUID.01H:ECX[21] indicates that the processor supports x2APIC and the extended
topology enumeration leaf (CPUID.0BH).
The extended topology enumeration leaf can be accessed by executing CPUID with
EAX = 0BH. Processors that do not support x2APIC may support CPUID leaf 0BH.
Software can detect the availability of the extended topology enumeration leaf (0BH)
by performing two steps:
CPUID.01H:ECX[21] indicates that the processor supports x2APIC and the extended
topology enumeration leaf (CPUID.0BH).
The extended topology enumeration leaf can be accessed by executing CPUID with
EAX = 0BH. Processors that do not support x2APIC may support CPUID leaf 0BH.
Software can detect the availability of the extended topology enumeration leaf (0BH)
by performing two steps:
•
Check maximum input value for basic CPUID information by executing CPUID
with EAX= 0. If CPUID.0H:EAX is greater than or equal or 11 (0BH), then proceed
to next step
with EAX= 0. If CPUID.0H:EAX is greater than or equal or 11 (0BH), then proceed
to next step
•
Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero.
If both of the above conditions are true, extended topology enumeration leaf is avail-
able. The presence of CPUID leaf 0BH in a processor does not guarantee support for
x2APIC. If CPUID.EAX=0BH, ECX=0H:EBX returns zero and maximum input value for
basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not supported
on that processor.
able. The presence of CPUID leaf 0BH in a processor does not guarantee support for
x2APIC. If CPUID.EAX=0BH, ECX=0H:EBX returns zero and maximum input value for
basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not supported
on that processor.