Intel 253668-032US User Manual
10-38 Vol. 3
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
10.6.5
Local Interrupt Acceptance
When a local interrupt is sent to the processor core, it is subject to the acceptance
criteria specified in the interrupt acceptance flow chart in
criteria specified in the interrupt acceptance flow chart in
. If the inter-
rupt is accepted, it is logged into the IRR register and handled by the processor
according to its priority (see
according to its priority (see
). If the interrupt is not accepted, it is sent back to the local APIC and retried.
10.7 ISSUING
INTERPROCESSOR
INTERRUPTS
The following sections describe the local APIC facilities that are provided for issuing
interprocessor interrupts (IPIs) from software. The primary local APIC facility for
issuing IPIs is the interrupt command register (ICR). The ICR can be used for the
following functions:
interprocessor interrupts (IPIs) from software. The primary local APIC facility for
issuing IPIs is the interrupt command register (ICR). The ICR can be used for the
following functions:
•
To send an interrupt to another processor.
•
To allow a processor to forward an interrupt that it received but did not service to
another processor for servicing.
another processor for servicing.
•
To direct the processor to interrupt itself (perform a self interrupt).
•
To deliver special IPIs, such as the start-up IPI (SIPI) message, to other
processors.
processors.
Interrupts generated with this facility are delivered to the other processors in the
system through the system bus (for Pentium 4 and Intel Xeon processors) or the
APIC bus (for P6 family and Pentium processors). The ability for a processor to send
a lowest priority IPI is model specific and should be avoided by BIOS and operating
system software.
system through the system bus (for Pentium 4 and Intel Xeon processors) or the
APIC bus (for P6 family and Pentium processors). The ability for a processor to send
a lowest priority IPI is model specific and should be avoided by BIOS and operating
system software.
10.7.1
Interrupt Command Register (ICR)
The interrupt command register (ICR) is a 64-bit local APIC register (see
) that allows software running on the processor to specify and send
interprocessor interrupts (IPIs) to other processors in the system.
To send an IPI, software must set up the ICR to indicate the type of IPI message to
be sent and the destination processor or processors. (All fields of the ICR are read-
write by software with the exception of the delivery status field, which is read-only.)
The act of writing to the low doubleword of the ICR causes the IPI to be sent.
To send an IPI, software must set up the ICR to indicate the type of IPI message to
be sent and the destination processor or processors. (All fields of the ICR are read-
write by software with the exception of the delivery status field, which is read-only.)
The act of writing to the low doubleword of the ICR causes the IPI to be sent.