Intel 253668-032US User Manual

Page of 806
10-46   Vol. 3
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
10.7.2 
Determining IPI Destination
The destination of an IPI can be one, all, or a subset (group) of the processors on the 
system bus. The sender of the IPI specifies the destination of an IPI with the 
following APIC registers and fields within the registers:
ICR Register — The following fields in the ICR register are used to specify the 
destination of an IPI:
— Destination Mode — Selects one of two destination modes (physical or 
logical).
— Destination Field — In physical destination mode, used to specify the APIC 
ID of the destination processor; in logical destination mode, used to specify a 
message destination address (MDA) that can be used to select specific 
processors in clusters.
— Destination Shorthand — A quick method of specifying all processors, all 
excluding self, or self as the destination.
— Delivery mode, Lowest Priority — Architecturally specifies that a lowest-
priority arbitration mechanism be used to select a destination processor from 
a specified group of processors. The ability of a processor to send a lowest 
priority IPI is model specific and should be avoided by BIOS and operating 
system software.
Local destination register (LDR) — Used in conjunction with the logical 
destination mode and MDAs to select the destination processors.
Destination format register (DFR) — Used in conjunction with the logical 
destination mode and MDAs to select the destination processors.
How the ICR, LDR, and DFR are used to select an IPI destination depends on the 
destination mode used: physical, logical, broadcast/self, or lowest-priority delivery 
mode. These destination modes are described in the following sections.
10.7.2.1   Physical Destination Mode
In physical destination mode, the destination processor is specified by its local APIC 
ID (see 
). For Pentium 4 and Intel Xeon processors, 
either a single destination (local APIC IDs 00H through FEH) or a broadcast to all 
APICs (the APIC ID is FFH) may be specified in physical destination mode. 
A broadcast IPI (bits 28-31 of the MDA are 1's) or I/O subsystem initiated interrupt 
with lowest priority delivery mode is not supported in physical destination mode and 
must not be configured by software. Also, for any non-broadcast IPI or I/O 
subsystem initiated interrupt with lowest priority delivery mode, software must 
ensure that APICs defined in the interrupt address are present and enabled to receive 
interrupts. 
For the P6 family and Pentium processors, a single destination is specified in physical 
destination mode with a local APIC ID of 0H through 0EH, allowing up to 15 local