Intel 253668-032US User Manual
Vol. 3 10-61
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
bit is cleared for edge-triggered interrupts and set for level-triggered interrupts. If a
TMR bit is set when an EOI cycle for its corresponding interrupt vector is generated,
an EOI message is sent to all I/O APICs.
TMR bit is set when an EOI cycle for its corresponding interrupt vector is generated,
an EOI message is sent to all I/O APICs.
10.9.5
Signaling Interrupt Servicing Completion
For all interrupts except those delivered with the NMI, SMI, INIT, ExtINT, the start-
up, or INIT-Deassert delivery mode, the interrupt handler must include a write to the
end-of-interrupt (EOI) register (see
up, or INIT-Deassert delivery mode, the interrupt handler must include a write to the
end-of-interrupt (EOI) register (see
). This write must occur at the end
of the handler routine, sometime before the IRET instruction. This action indicates
that the servicing of the current interrupt is complete and the local APIC can issue the
next interrupt from the ISR.
that the servicing of the current interrupt is complete and the local APIC can issue the
next interrupt from the ISR.
Upon receiving and EOI, the APIC clears the highest priority bit in the ISR and
dispatches the next highest priority interrupt to the processor. If the terminated
interrupt was a level-triggered interrupt, the local APIC also sends an end-of-inter-
rupt message to all I/O APICs.
dispatches the next highest priority interrupt to the processor. If the terminated
interrupt was a level-triggered interrupt, the local APIC also sends an end-of-inter-
rupt message to all I/O APICs.
10.9.5.1 Signaling Interrupt Servicing Completion in x2APIC Mode
In the x2APIC mode, the write of a zero value to EOI register is enforced. Writes of a
non-zero value to the EOI register in x2APIC mode will raise a GP fault. System soft-
ware continues to have to perform the EOI write to indicate interrupt service comple-
tion. But in x2APIC mode, the EOI write is with a value of zero.
non-zero value to the EOI register in x2APIC mode will raise a GP fault. System soft-
ware continues to have to perform the EOI write to indicate interrupt service comple-
tion. But in x2APIC mode, the EOI write is with a value of zero.
10.9.6
Task Priority in IA-32e Mode
In IA-32e mode, operating systems can manage the 16 priority classes of external
interrupts (see
interrupts (see
) explicitly
using the task priority register (TPR). Operating systems can use the TPR to tempo-
rarily block specific (low-priority) interrupts from interrupting a high-priority task.
This is done by loading TPR with a value corresponding to the highest-priority inter-
rupt that is to be blocked. For example:
rarily block specific (low-priority) interrupts from interrupting a high-priority task.
This is done by loading TPR with a value corresponding to the highest-priority inter-
rupt that is to be blocked. For example:
Figure 10-29. EOI Register
31
0
Address: 0FEE0 00B0H
Value after reset: 0H
Value after reset: 0H