Intel 253668-032US User Manual

Vol. 3 10-67

ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)

destination mode and only the processor in the system that has the matching
APIC ID is considered for delivery of that interrupt (this means no re-direction).
If RH is 1 and DM is 1, the Destination ID Field is interpreted as in logical
destination mode and the redirection is limited to only those processors that are
part of the logical group of processors based on the processor’s logical APIC ID
and the Destination ID field in the message. The logical group of processors
consists of those identified by matching the 8-bit Destination ID with the logical
destination identified by the Destination Format Register and the Logical
Destination Register in each local APIC. The details are similar to those described
in

Section 10.7.2, “Determining IPI Destination.”

If RH is 0, then the DM bit is

ignored and the message is sent ahead independent of whether the physical or
logical destination mode is used.

10.12.2 Message Data Register Format

The layout of the Message Data Register is shown in

Figure 10-33

Figure 10-33. Layout of the MSI Message Data Register

Reserved

Vector

Delivery Mode

001 - Lowest Priority
010 - SMI
011 - Reserved

101 - INIT
110 - Reserved
111 - ExtINT

Trigger Mode

0 - Edge
1 - Level

Level for Trigger Mode = 0

X - Don’t care

Level for Trigger Mode = 1

0 - Deassert
1 - Assert

000 - Fixed

100 - NMI

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