Intel 253668-032US User Manual
11-20 Vol. 3
MEMORY CACHE CONTROL
page-table entries) permit caching in an external L2 cache to be controlled on a
page-by-page basis, consistent with the control exercised on the L1 cache of
these processors. The P6 and more recent processor families do not provide
these pins because the L2 cache in internal to the chip package.
page-by-page basis, consistent with the control exercised on the L1 cache of
these processors. The P6 and more recent processor families do not provide
these pins because the L2 cache in internal to the chip package.
11.5.2
Precedence of Cache Controls
The cache control flags and MTRRs operate hierarchically for restricting caching. That
is, if the CD flag is set, caching is prevented globally (see Table 11-5). If the CD flag
is clear, the page-level cache control flags and/or the MTRRs can be used to restrict
caching. If there is an overlap of page-level and MTRR caching controls, the mecha-
nism that prevents caching has precedence. For example, if an MTRR makes a region
of system memory uncacheable, a page-level caching control cannot be used to
enable caching for a page in that region. The converse is also true; that is, if a page-
level caching control designates a page as uncacheable, an MTRR cannot be used to
make the page cacheable.
In cases where there is a overlap in the assignment of the write-back and write-
through caching policies to a page and a region of memory, the write-through policy
takes precedence. The write-combining policy (which can only be assigned through
an MTRR or the PAT) takes precedence over either write-through or write-back.
The selection of memory types at the page level varies depending on whether PAT is
being used to select memory types for pages, as described in the following sections.
On processors based on Intel NetBurst microarchitecture, the third-level cache can
be disabled by bit 6 of the IA32_MISC_ENABLE MSR. Using IA32_MISC_ENALBES[bit
6] takes precedence over the CD flag, MTRRs, and PAT for the L3 cache in those
processors. That is, when the third-level cache disable flag is set (cache disabled),
the other cache controls have no affect on the L3 cache; when the flag is clear
(enabled), the cache controls have the same affect on the L3 cache as they have on
the L1 and L2 caches.
IA32_MISC_ENALBES[bit 6] is not supported in Intel Core i7 processors, nor proces-
sors based on Intel Core, and Intel Atom microarchitectures.
is, if the CD flag is set, caching is prevented globally (see Table 11-5). If the CD flag
is clear, the page-level cache control flags and/or the MTRRs can be used to restrict
caching. If there is an overlap of page-level and MTRR caching controls, the mecha-
nism that prevents caching has precedence. For example, if an MTRR makes a region
of system memory uncacheable, a page-level caching control cannot be used to
enable caching for a page in that region. The converse is also true; that is, if a page-
level caching control designates a page as uncacheable, an MTRR cannot be used to
make the page cacheable.
In cases where there is a overlap in the assignment of the write-back and write-
through caching policies to a page and a region of memory, the write-through policy
takes precedence. The write-combining policy (which can only be assigned through
an MTRR or the PAT) takes precedence over either write-through or write-back.
The selection of memory types at the page level varies depending on whether PAT is
being used to select memory types for pages, as described in the following sections.
On processors based on Intel NetBurst microarchitecture, the third-level cache can
be disabled by bit 6 of the IA32_MISC_ENABLE MSR. Using IA32_MISC_ENALBES[bit
6] takes precedence over the CD flag, MTRRs, and PAT for the L3 cache in those
processors. That is, when the third-level cache disable flag is set (cache disabled),
the other cache controls have no affect on the L3 cache; when the flag is clear
(enabled), the cache controls have the same affect on the L3 cache as they have on
the L1 and L2 caches.
IA32_MISC_ENALBES[bit 6] is not supported in Intel Core i7 processors, nor proces-
sors based on Intel Core, and Intel Atom microarchitectures.
11.5.2.1 Selecting Memory Types for Pentium Pro and Pentium II
Processors
The Pentium Pro and Pentium II processors do not support the PAT. Here, the effec-
tive memory type for a page is selected with the MTRRs and the PCD and PWT bits in
the page-table or page-directory entry for the page. Table 11-6 describes the
mapping of MTRR memory types and page-level caching attributes to effective
memory types, when normal caching is in effect (the CD and NW flags in control
register CR0 are clear). Combinations that appear in gray are implementation-
defined for the Pentium Pro and Pentium II processors. System designers are encour-
aged to avoid these implementation-defined combinations.
tive memory type for a page is selected with the MTRRs and the PCD and PWT bits in
the page-table or page-directory entry for the page. Table 11-6 describes the
mapping of MTRR memory types and page-level caching attributes to effective
memory types, when normal caching is in effect (the CD and NW flags in control
register CR0 are clear). Combinations that appear in gray are implementation-
defined for the Pentium Pro and Pentium II processors. System designers are encour-
aged to avoid these implementation-defined combinations.