Intel 253668-032US User Manual
Vol. 3 14-1
CHAPTER 14
POWER AND THERMAL MANAGEMENT
This chapter describes facilities of Intel 64 and IA-32 architecture used for power
management and thermal monitoring.
management and thermal monitoring.
14.1
ENHANCED INTEL SPEEDSTEP
®
TECHNOLOGY
Enhanced Intel SpeedStep
®
Technology was introduced in the Pentium M processor;
it is available in Pentium 4, Intel Xeon, Intel
®
Core™ Solo, Intel
®
Core™ Duo, Intel
®
Atom™ and Intel
®
Core™2 Duo processors. The technology manages processor
power consumption using performance state transitions. These states are defined as
discrete operating points associated with different frequencies.
Enhanced Intel SpeedStep Technology differs from previous generations of Intel
SpeedStep Technology in two ways:
discrete operating points associated with different frequencies.
Enhanced Intel SpeedStep Technology differs from previous generations of Intel
SpeedStep Technology in two ways:
•
Centralization of the control mechanism and software interface in the processor
by using model-specific registers.
by using model-specific registers.
•
Reduced hardware overhead; this permits more frequent performance state
transitions.
transitions.
Previous generations of the Intel SpeedStep Technology require processors to be a
deep sleep state, holding off bus master transfers for the duration of a performance
state transition. Performance state transitions under the Enhanced Intel SpeedStep
Technology are discrete transitions to a new target frequency.
Support is indicated by CPUID, using ECX feature bit 07. Enhanced Intel SpeedStep
Technology is enabled by setting IA32_MISC_ENABLE MSR, bit 16. On reset, bit 16 of
IA32_MISC_ENABLE MSR is cleared.
deep sleep state, holding off bus master transfers for the duration of a performance
state transition. Performance state transitions under the Enhanced Intel SpeedStep
Technology are discrete transitions to a new target frequency.
Support is indicated by CPUID, using ECX feature bit 07. Enhanced Intel SpeedStep
Technology is enabled by setting IA32_MISC_ENABLE MSR, bit 16. On reset, bit 16 of
IA32_MISC_ENABLE MSR is cleared.
14.1.1
Software Interface For Initiating Performance State
Transitions
State transitions are initiated by writing a 16-bit value to the IA32_PERF_CTL
register, see Figure 14-2. If a transition is already in progress, transition to a new
value will subsequently take effect.
Reads of IA32_PERF_CTL determine the last targeted operating point. The current
operating point can be read from IA32_PERF_STATUS. IA32_PERF_STATUS is
updated dynamically.
The 16-bit encoding that defines valid operating points is model-specific. Applications
and performance tools are not expected to use either IA32_PERF_CTL or
IA32_PERF_STATUS and should treat both as reserved. Performance monitoring
register, see Figure 14-2. If a transition is already in progress, transition to a new
value will subsequently take effect.
Reads of IA32_PERF_CTL determine the last targeted operating point. The current
operating point can be read from IA32_PERF_STATUS. IA32_PERF_STATUS is
updated dynamically.
The 16-bit encoding that defines valid operating points is model-specific. Applications
and performance tools are not expected to use either IA32_PERF_CTL or
IA32_PERF_STATUS and should treat both as reserved. Performance monitoring