Intel 253668-032US User Manual
15-12 Vol. 3
MACHINE-CHECK ARCHITECTURE
15.3.2.4 IA32_MC
i
_MISC MSRs
The IA32_MCi_MISC MSR contains additional information describing the
machine-check error if the MISCV flag in the IA32_MCi_STATUS register is
set. The IA32_MCi_MISC_MSR is either not implemented or does not contain
additional information if the MISCV flag in the IA32_MCi_STATUS register is
clear.
When not implemented in the processor, all reads and writes to this MSR will
When not implemented in the processor, all reads and writes to this MSR will
cause a general protection exception. When implemented in a processor,
these registers can be cleared by explicitly writing all 0s to them; writing 1s
to them causes a general-protection exception to be generated. This register
is not implemented in any of the error-reporting register banks for the P6
family processors.
If both MISCV and
If both MISCV and
IA32_MCG_CAP[24]
are set, the IA32_MCi_MISC_MSR is
defined according to Figure 15-7 to support software recovery of uncor-
rected errors (see Section 15.6):
Figure 15-6. IA32_MCi_ADDR MSR
Address
63
0
Reserved
35
36
Address
*
63
0
Processor Without Support For Intel 64 Architecture
Processor With Support for Intel 64 Architecture
*
Useful bits in this field depend on the address methodology in use when the
the register state is saved.