Intel 253668-032US User Manual
15-22 Vol. 3
MACHINE-CHECK ARCHITECTURE
b. Each thread examines IA32_MCi_CTL2[30] indicator for each bank to
determine if another thread has already claimed ownership of that bank.
•
If IA32_MCi_CTL2[30] had been set by another thread. This thread can
not own bank i and should proceed to step b. and examine the next
machine check bank until all of the machine check banks are exhausted.
machine check bank until all of the machine check banks are exhausted.
•
If IA32_MCi_CTL2[30] = 0, proceed to step c.
c. Check whether writing a 1 into IA32_MCi_CTL2[30] can return with 1 on a
subsequent read to determine this bank can support CMCI.
•
If IA32_MCi_CTL2[30] = 0, this bank does not support CMCI. This thread
can not own bank i and should proceed to step b. and examine the next
machine check bank until all of the machine check banks are exhausted.
machine check bank until all of the machine check banks are exhausted.
•
If IA32_MCi_CTL2[30] = 1, modify the per-thread data structure to
indicate this thread claims ownership to the MC bank; proceed to initialize
the error threshold count (bits 15:0) of that bank as described in Chapter
15, “CMCI Threshold Management”. Then proceed to step b. and examine
the next machine check bank until all of the machine check banks are
exhausted.
the error threshold count (bits 15:0) of that bank as described in Chapter
15, “CMCI Threshold Management”. Then proceed to step b. and examine
the next machine check bank until all of the machine check banks are
exhausted.
•
After the thread has examined all of the machine check banks, it sees if it owns
any MC banks to service CMCI. If any bank has been claimed by this thread:
— Ensure that the CMCI interrupt handler has been set up as described in
any MC banks to service CMCI. If any bank has been claimed by this thread:
— Ensure that the CMCI interrupt handler has been set up as described in
— Initialize the CMCI LVT entry, as described in Chapter 15, “CMCI Local APIC
— Log and clear all of IA32_MCi_Status registers for the banks that this thread
owns. This will allow new errors to be logged.
15.5.2.2 CMCI Threshold Management
The Corrected MC error threshold field, IA32_MCi_CTL2[15:0], is architec-
turally defined. Specifically, all these bits are writable by software, but
different processor implementations may choose to implement less than 15
bits as threshold for the overflow comparison with
IA32_MCi_STATUS[52:38]. The following describes techniques that soft-
ware can manage CMCI threshold to be compatible with changes in imple-
mentation characteristics:
•
Software can set the initial threshold value to 1 by writing 1 to
IA32_MCi_CTL2[15:0]. This will cause overflow
condition on every
corrected MC error and generates a CMCI interrupt.
•
To increase the threshold and reduce the frequency of CMCI servicing:
a. Find the maximum threshold value a given processor implementation
a. Find the maximum threshold value a given processor implementation
supports. The steps are: