Intel 253668-032US User Manual
15-36 Vol. 3
MACHINE-CHECK ARCHITECTURE
IA32_MCG_STATUS register for the memory scrubbing and L3 explicit write-
back errors on both the reporting and non-reporting logical processors.
15.9.3.2 Architecturally Defined SRAR Errors
The following two SRAR errors are architecturally defined.
•
UCR Errors detected on data load; and
•
UCR Errors detected on instruction fetch.
The MCA error code encodings for these two architecturally-defined UCR
errors corresponds to sub-classes of compound MCA error codes (see Table
Table 15-17. IA32_MCG_STATUS Flag Indication for SRAO Errors
SRAO Type
Reporting Logical Processors
Non-reporting Logical Processors
RIPV
EIPV
RIPV
EIPV
Memory Scrubbing
1
0
1
0
L3 Explicit Writeback
1
0
1
0
Table 15-18. MCA Compound Error Code Encoding for SRAR Errors
Type
MCACOD Value MCA Error Code Encoding
1
NOTES:
1. Note that for both of these errors the correction report filtering (F) bit (bit 12) of the MCA error is
0, indicating "normal" filtering.
Data Load
0x134
0000_0001_0011_0100
000F 0001 RRRR TTLL (Cache Hierarchy Error), where
Request subfield RRRR = 0011B (Data Load)
Transaction Type subfield TT= 01B (Data)
Level subfield LL = 00B (Level 0)
000F 0001 RRRR TTLL (Cache Hierarchy Error), where
Request subfield RRRR = 0011B (Data Load)
Transaction Type subfield TT= 01B (Data)
Level subfield LL = 00B (Level 0)
Instruction Fetch
0x150
0000_0001_0101_0000
000F 0001 RRRR TTLL (Cache Hierarchy Error), where
Request subfield RRRR = 0101B (Instruction Fetch)
Transaction Type subfield TT= 00B (Instruction)
Level subfield LL = 00B (Level 0)
000F 0001 RRRR TTLL (Cache Hierarchy Error), where
Request subfield RRRR = 0101B (Instruction Fetch)
Transaction Type subfield TT= 00B (Instruction)
Level subfield LL = 00B (Level 0)