Intel 253668-032US User Manual
Vol. 3 16-13
DEBUGGING, PROFILING BRANCHES AND TIME-STAMP COUNTER
single-step trap does not occur until after the instruction that follows the POPF
instruction.
The processor clears the TF flag before calling the exception handler. If the TF flag
was set in a TSS at the time of a task switch, the exception occurs after the first
instruction is executed in the new task.
The TF flag normally is not cleared by privilege changes inside a task. The INT n and
INTO instructions, however, do clear this flag. Therefore, software debuggers that
single-step code must recognize and emulate INT n or INTO instructions rather than
executing them directly. To maintain protection, the operating system should check
the CPL after any single-step trap to see if single stepping should continue at the
current privilege level.
The interrupt priorities guarantee that, if an external interrupt occurs, single step-
ping stops. When both an external interrupt and a single-step interrupt occur
together, the single-step interrupt is processed first. This operation clears the TF flag.
After saving the return address or switching tasks, the external interrupt input is
examined before the first instruction of the single-step handler executes. If the
external interrupt is still pending, then it is serviced. The external interrupt handler
does not run in single-step mode. To single step an interrupt handler, single step an
INT n instruction that calls the interrupt handler.
instruction.
The processor clears the TF flag before calling the exception handler. If the TF flag
was set in a TSS at the time of a task switch, the exception occurs after the first
instruction is executed in the new task.
The TF flag normally is not cleared by privilege changes inside a task. The INT n and
INTO instructions, however, do clear this flag. Therefore, software debuggers that
single-step code must recognize and emulate INT n or INTO instructions rather than
executing them directly. To maintain protection, the operating system should check
the CPL after any single-step trap to see if single stepping should continue at the
current privilege level.
The interrupt priorities guarantee that, if an external interrupt occurs, single step-
ping stops. When both an external interrupt and a single-step interrupt occur
together, the single-step interrupt is processed first. This operation clears the TF flag.
After saving the return address or switching tasks, the external interrupt input is
examined before the first instruction of the single-step handler executes. If the
external interrupt is still pending, then it is serviced. The external interrupt handler
does not run in single-step mode. To single step an interrupt handler, single step an
INT n instruction that calls the interrupt handler.
16.3.1.5 Task-Switch Exception Condition
The processor generates a debug exception after a task switch if the T flag of the new
task's TSS is set. This exception is generated after program control has passed to the
new task, and prior to the execution of the first instruction of that task. The exception
handler can detect this condition by examining the BT flag of the DR6 register.
If entry 1 (#DB) in the IDT is a task gate, the T bit of the corresponding TSS should
not be set. Failure to observe this rule will put the processor in a loop.
task's TSS is set. This exception is generated after program control has passed to the
new task, and prior to the execution of the first instruction of that task. The exception
handler can detect this condition by examining the BT flag of the DR6 register.
If entry 1 (#DB) in the IDT is a task gate, the T bit of the corresponding TSS should
not be set. Failure to observe this rule will put the processor in a loop.
16.3.2
Breakpoint Exception (#BP)—Interrupt Vector 3
The breakpoint exception (interrupt 3) is caused by execution of an INT 3 instruction.
See Chapter 6, “Interrupt 3—Breakpoint Exception (#BP).” Debuggers use break
exceptions in the same way that they use the breakpoint registers; that is, as a
mechanism for suspending program execution to examine registers and memory
locations. With earlier IA-32 processors, breakpoint exceptions are used extensively
for setting instruction breakpoints.
With the Intel386 and later IA-32 processors, it is more convenient to set break-
points with the breakpoint-address registers (DR0 through DR3). However, the
breakpoint exception still is useful for breakpointing debuggers, because a break-
point exception can call a separate exception handler. The breakpoint exception is
also useful when it is necessary to set more breakpoints than there are debug regis-
ters or when breakpoints are being placed in the source code of a program under
development.
See Chapter 6, “Interrupt 3—Breakpoint Exception (#BP).” Debuggers use break
exceptions in the same way that they use the breakpoint registers; that is, as a
mechanism for suspending program execution to examine registers and memory
locations. With earlier IA-32 processors, breakpoint exceptions are used extensively
for setting instruction breakpoints.
With the Intel386 and later IA-32 processors, it is more convenient to set break-
points with the breakpoint-address registers (DR0 through DR3). However, the
breakpoint exception still is useful for breakpointing debuggers, because a break-
point exception can call a separate exception handler. The breakpoint exception is
also useful when it is necessary to set more breakpoints than there are debug regis-
ters or when breakpoints are being placed in the source code of a program under
development.