Intel 253668-032US User Manual
Vol. 3 16-31
DEBUGGING, PROFILING BRANCHES AND TIME-STAMP COUNTER
16.4.9.5 Writing the DS Interrupt Service Routine
The BTS, non-precise event-based sampling, and PEBS facilities share the same
interrupt vector and interrupt service routine (called the debug store interrupt
service routine or DS ISR). To handle BTS, non-precise event-based sampling, and
PEBS interrupts: separate handler routines must be included in the DS ISR. Use the
following guidelines when writing a DS ISR to handle BTS, non-precise event-based
sampling, and/or PEBS interrupts.
interrupt vector and interrupt service routine (called the debug store interrupt
service routine or DS ISR). To handle BTS, non-precise event-based sampling, and
PEBS interrupts: separate handler routines must be included in the DS ISR. Use the
following guidelines when writing a DS ISR to handle BTS, non-precise event-based
sampling, and/or PEBS interrupts.
•
The DS interrupt service routine (ISR) must be part of a kernel driver and operate
at a current privilege level of 0 to secure the buffer storage area.
at a current privilege level of 0 to secure the buffer storage area.
•
Because the BTS, non-precise event-based sampling, and PEBS facilities share
the same interrupt vector, the DS ISR must check for all the possible causes of
interrupts from these facilities and pass control on to the appropriate handler.
the same interrupt vector, the DS ISR must check for all the possible causes of
interrupts from these facilities and pass control on to the appropriate handler.
BTS and PEBS buffer overflow would be the sources of the interrupt if the buffer
index matches/exceeds the interrupt threshold specified. Detection of non-
precise event-based sampling as the source of the interrupt is accomplished by
checking for counter overflow.
index matches/exceeds the interrupt threshold specified. Detection of non-
precise event-based sampling as the source of the interrupt is accomplished by
checking for counter overflow.
•
There must be separate save areas, buffers, and state for each processor in an
MP system.
MP system.
•
Upon entering the ISR, branch trace messages and PEBS should be disabled to
prevent race conditions during access to the DS save area. This is done by
clearing TR flag in the IA32_DEBUGCTL (or MSR_DEBUGCTLA MSR) and by
clearing the precise event enable flag in the MSR_PEBS_ENABLE MSR. These
settings should be restored to their original values when exiting the ISR.
prevent race conditions during access to the DS save area. This is done by
clearing TR flag in the IA32_DEBUGCTL (or MSR_DEBUGCTLA MSR) and by
clearing the precise event enable flag in the MSR_PEBS_ENABLE MSR. These
settings should be restored to their original values when exiting the ISR.
•
The processor will not disable the DS save area when the buffer is full and the
circular mode has not been selected. The current DS setting must be retained
and restored by the ISR on exit.
circular mode has not been selected. The current DS setting must be retained
and restored by the ISR on exit.
•
After reading the data in the appropriate buffer, up to but not including the
current index into the buffer, the ISR must reset the buffer index to the beginning
of the buffer. Otherwise, everything up to the index will look like new entries upon
the next invocation of the ISR.
current index into the buffer, the ISR must reset the buffer index to the beginning
of the buffer. Otherwise, everything up to the index will look like new entries upon
the next invocation of the ISR.
1
1
1
0
1
Store BTMs with CPL > 0 in the
BTS buffer; generate an
interrupt when the buffer is
nearly full
1
1
0
1
1
Store BTMs with CPL = 0 in the
BTS buffer; generate an
interrupt when the buffer is
nearly full
Table 16-5. CPL-Qualified Branch Trace Store Encodings (Contd.)
TR
BTS
BTS_OFF_OS
BTS_OFF_USR
BTINT
Description