Intel 253668-032US User Manual
16-36 Vol. 3
DEBUGGING, PROFILING BRANCHES AND TIME-STAMP COUNTER
16.7
LAST BRANCH, INTERRUPT, AND EXCEPTION
RECORDING (PROCESSORS BASED ON INTEL
NETBURST
®
MICROARCHITECTURE)
Pentium 4 and Intel Xeon processors based on Intel NetBurst microarchitecture
provide the following methods for recording taken branches, interrupts and excep-
tions:
provide the following methods for recording taken branches, interrupts and excep-
tions:
•
Store branch records in the last branch record (LBR) stack MSRs for the most
recent taken branches, interrupts, and/or exceptions in MSRs. A branch record
consist of a branch-from and a branch-to instruction address.
recent taken branches, interrupts, and/or exceptions in MSRs. A branch record
consist of a branch-from and a branch-to instruction address.
•
Send the branch records out on the system bus as branch trace messages
(BTMs).
(BTMs).
•
Log BTMs in a memory-resident branch trace store (BTS) buffer.
To support these functions, the processor provides the following MSRs and related
facilities:
facilities:
•
MSR_DEBUGCTLA MSR — Enables last branch, interrupt, and exception
recording; single-stepping on taken branches; branch trace messages (BTMs);
and branch trace store (BTS). This register is named DebugCtlMSR in the P6
family processors.
recording; single-stepping on taken branches; branch trace messages (BTMs);
and branch trace store (BTS). This register is named DebugCtlMSR in the P6
family processors.
•
Debug store (DS) feature flag (CPUID.1:EDX.DS[bit 21]) — Indicates that
the processor provides the debug store (DS) mechanism, which allows BTMs to
be stored in a memory-resident BTS buffer.
the processor provides the debug store (DS) mechanism, which allows BTMs to
be stored in a memory-resident BTS buffer.
•
CPL-qualified debug store (DS) feature flag (CPUID.1:ECX.DS-CPL[bit
4]) — Indicates that the processor provides a CPL-qualified debug store (DS)
mechanism, which allows software to selectively skip sending and storing BTMs,
according to specified current privilege level settings, into a memory-resident
BTS buffer.
4]) — Indicates that the processor provides a CPL-qualified debug store (DS)
mechanism, which allows software to selectively skip sending and storing BTMs,
according to specified current privilege level settings, into a memory-resident
BTS buffer.
JCC
2
R/W
When set, do not capture conditional branches
NEAR_REL_CALL
3
R/W
When set, do not capture near relative calls
NEAR_IND_CALL
4
R/W
When set, do not capture near indirect calls
NEAR_RET
5
R/W
When set, do not capture near returns
NEAR_IND_JMP
6
R/W
When set, do not capture near indirect jumps
NEAR_REL_JMP
7
R/W
When set, do not capture near relative jumps
FAR_BRANCH
8
R/W
When set, do not capture far branches
Reserved
63:9
Must be zero
Table 16-9. MSR_LBR_SELECT (Contd.)
Bit Field
Bit Offset
Access
Description