Intel 253668-032US User Manual
17-18 Vol. 3
8086 EMULATION
in the previous paragraphs. These sections describe three possible types of interrupt
and exception handlers:
and exception handlers:
•
Protected-mode interrupt and exceptions handlers — These are the
standard handlers that the processor calls through the protected-mode IDT.
standard handlers that the processor calls through the protected-mode IDT.
•
Virtual-8086 monitor interrupt and exception handlers — These handlers
are resident in the virtual-8086 monitor, and they are commonly accessed
through a general-protection exception (#GP, interrupt 13) that is directed to the
protected-mode general-protection exception handler.
are resident in the virtual-8086 monitor, and they are commonly accessed
through a general-protection exception (#GP, interrupt 13) that is directed to the
protected-mode general-protection exception handler.
•
8086 program interrupt and exception handlers — These handlers are part
of the 8086 program that is running in virtual-8086 mode.
of the 8086 program that is running in virtual-8086 mode.
The following sections describe how these handlers are used, depending on the
selected class and method of interrupt and exception handling.
selected class and method of interrupt and exception handling.
17.3.1
Class 1—Hardware Interrupt and Exception Handling in
Virtual-8086 Mode
In virtual-8086 mode, the Pentium, P6 family, Pentium 4, and Intel Xeon processors
handle hardware interrupts and exceptions in the same manner as they are handled
by the Intel486 and Intel386 processors. They invoke the protected-mode interrupt
or exception handler that the interrupt or exception vector points to in the IDT. Here,
the IDT entry must contain either a 32-bit trap or interrupt gate or a task gate. The
following sections describe various ways that a virtual-8086 mode interrupt or excep-
tion can be handled after the protected-mode handler has been invoked.
See Section 17.3.2, “Class 2—Maskable Hardware Interrupt Handling in Virtual-8086
Mode Using the Virtual Interrupt Mechanism”, for a description of the virtual interrupt
mechanism that is available for handling maskable hardware interrupts while in
virtual-8086 mode. When this mechanism is either not available or not enabled,
maskable hardware interrupts are handled in the same manner as exceptions, as
described in the following sections.
handle hardware interrupts and exceptions in the same manner as they are handled
by the Intel486 and Intel386 processors. They invoke the protected-mode interrupt
or exception handler that the interrupt or exception vector points to in the IDT. Here,
the IDT entry must contain either a 32-bit trap or interrupt gate or a task gate. The
following sections describe various ways that a virtual-8086 mode interrupt or excep-
tion can be handled after the protected-mode handler has been invoked.
See Section 17.3.2, “Class 2—Maskable Hardware Interrupt Handling in Virtual-8086
Mode Using the Virtual Interrupt Mechanism”, for a description of the virtual interrupt
mechanism that is available for handling maskable hardware interrupts while in
virtual-8086 mode. When this mechanism is either not available or not enabled,
maskable hardware interrupts are handled in the same manner as exceptions, as
described in the following sections.
17.3.1.1 Handling an Interrupt or Exception Through a Protected-Mode
Trap or Interrupt Gate
When an interrupt or exception vector points to a 32-bit trap or interrupt gate in the
IDT, the gate must in turn point to a nonconforming, privilege-level 0, code segment.
When accessing this code segment, processor performs the following steps.
1. Switches to 32-bit protected mode and privilege level 0.
2. Saves the state of the processor on the privilege-level 0 stack. The states of the
IDT, the gate must in turn point to a nonconforming, privilege-level 0, code segment.
When accessing this code segment, processor performs the following steps.
1. Switches to 32-bit protected mode and privilege level 0.
2. Saves the state of the processor on the privilege-level 0 stack. The states of the
EIP, CS, EFLAGS, ESP, SS, ES, DS, FS, and GS registers are saved (see
Figure 17-4).
Figure 17-4).
3. Clears the segment registers. Saving the DS, ES, FS, and GS registers on the
stack and then clearing the registers lets the interrupt or exception handler safely