Intel 253668-032US User Manual
Vol. 3 19-27
ARCHITECTURE COMPATIBILITY
19.22.4 Changes in Segment Descriptor Loads
On the Intel386 processor, loading a segment descriptor always causes a locked read
and write to set the accessed bit of the descriptor. On the P6 family, Pentium, and
Intel486 processors, the locked read and write occur only if the bit is not already set.
and write to set the accessed bit of the descriptor. On the P6 family, Pentium, and
Intel486 processors, the locked read and write occur only if the bit is not already set.
19.23 DEBUG
FACILITIES
The P6 family and Pentium processors include extensions to the Intel486 processor
debugging support for breakpoints. To use the new breakpoint features, it is neces-
sary to set the DE flag in control register CR4.
debugging support for breakpoints. To use the new breakpoint features, it is neces-
sary to set the DE flag in control register CR4.
19.23.1 Differences in Debug Register DR6
It is not possible to write a 1 to reserved bit 12 in debug status register DR6 on the
P6 family and Pentium processors; however, it is possible to write a 1 in this bit on the
Intel486 processor. See Table 9-1 for the different setting of this register following a
power-up or hardware reset.
P6 family and Pentium processors; however, it is possible to write a 1 in this bit on the
Intel486 processor. See Table 9-1 for the different setting of this register following a
power-up or hardware reset.
19.23.2 Differences in Debug Register DR7
The P6 family and Pentium processors determines the type of breakpoint access by
the R/W0 through R/W3 fields in debug control register DR7 as follows:
00
the R/W0 through R/W3 fields in debug control register DR7 as follows:
00
Break on instruction execution only.
01
Break on data writes only.
10
Undefined if the DE flag in control register CR4 is cleared; break on I/O reads
or writes but not instruction fetches if the DE flag in control register CR4 is
set.
or writes but not instruction fetches if the DE flag in control register CR4 is
set.
11
Break on data reads or writes but not instruction fetches.
On the P6 family and Pentium processors, reserved bits 11, 12, 14 and 15 are hard-
wired to 0. On the Intel486 processor, however, bit 12 can be set. See Table 9-1 for
the different settings of this register following a power-up or hardware reset.
wired to 0. On the Intel486 processor, however, bit 12 can be set. See Table 9-1 for
the different settings of this register following a power-up or hardware reset.
19.23.3 Debug Registers DR4 and DR5
Although the DR4 and DR5 registers are documented as reserved, previous genera-
tions of processors aliased references to these registers to debug registers DR6 and
DR7, respectively. When debug extensions are not enabled (the DE flag in control
register CR4 is cleared), the P6 family and Pentium processors remain compatible
with existing software by allowing these aliased references. When debug extensions
tions of processors aliased references to these registers to debug registers DR6 and
DR7, respectively. When debug extensions are not enabled (the DE flag in control
register CR4 is cleared), the P6 family and Pentium processors remain compatible
with existing software by allowing these aliased references. When debug extensions