Intel 253668-032US User Manual
19-30 Vol. 3
ARCHITECTURE COMPATIBILITY
19.25.1 Machine-Check
Architecture
The Pentium Pro processor introduced a new architecture to the IA-32 for handling
and reporting on machine-check exceptions. This machine-check architecture
(described in detail in Chapter 15, “Machine-Check Architecture”) greatly expands
the ability of the processor to report on internal hardware errors.
and reporting on machine-check exceptions. This machine-check architecture
(described in detail in Chapter 15, “Machine-Check Architecture”) greatly expands
the ability of the processor to report on internal hardware errors.
19.25.2 Priority OF Exceptions
The priority of exceptions are broken down into several major categories:
1. Traps on the previous instruction
2. External interrupts
3. Faults on fetching the next instruction
4. Faults in decoding the next instruction
5. Faults on executing an instruction
There are no changes in the priority of these major categories between the different
processors, however, exceptions within these categories are implementation depen-
dent and may change from processor to processor.
1. Traps on the previous instruction
2. External interrupts
3. Faults on fetching the next instruction
4. Faults in decoding the next instruction
5. Faults on executing an instruction
There are no changes in the priority of these major categories between the different
processors, however, exceptions within these categories are implementation depen-
dent and may change from processor to processor.
19.26 INTERRUPTS
The following differences in handling interrupts are found among the IA-32
processors.
19.26.1 Interrupt Propagation Delay
External hardware interrupts may be recognized on different instruction boundaries
on the P6 family, Pentium, Intel486, and Intel386 processors, due to the superscaler
designs of the P6 family and Pentium processors. Therefore, the EIP pushed onto the
stack when servicing an interrupt may be different for the P6 family, Pentium,
Intel486, and Intel386 processors.
on the P6 family, Pentium, Intel486, and Intel386 processors, due to the superscaler
designs of the P6 family and Pentium processors. Therefore, the EIP pushed onto the
stack when servicing an interrupt may be different for the P6 family, Pentium,
Intel486, and Intel386 processors.
19.26.2 NMI
Interrupts
After an NMI interrupt is recognized by the P6 family, Pentium, Intel486, Intel386,
and Intel 286 processors, the NMI interrupt is masked until the first IRET instruction
is executed, unlike the 8086 processor.
and Intel 286 processors, the NMI interrupt is masked until the first IRET instruction
is executed, unlike the 8086 processor.