Intel 253668-032US User Manual
Vol. 3 19-37
ARCHITECTURE COMPATIBILITY
19.30.3 Enabling and Disabling Paging
Paging is enabled and disabled by loading a value into control register CR0 that modi-
fies the PG flag. For backward and forward compatibility with all IA-32 processors,
Intel recommends that the following operations be performed when enabling or
disabling paging:
1. Execute a MOV CR0, REG instruction to either set (enable paging) or clear
fies the PG flag. For backward and forward compatibility with all IA-32 processors,
Intel recommends that the following operations be performed when enabling or
disabling paging:
1. Execute a MOV CR0, REG instruction to either set (enable paging) or clear
(disable paging) the PG flag.
2. Execute a near JMP instruction.
The sequence bounded by the MOV and JMP instructions should be identity mapped
(that is, the instructions should reside on a page whose linear and physical addresses
are identical).
For the P6 family processors, the MOV CR0, REG instruction is serializing, so the
jump operation is not required. However, for backwards compatibility, the JMP
instruction should still be included.
The sequence bounded by the MOV and JMP instructions should be identity mapped
(that is, the instructions should reside on a page whose linear and physical addresses
are identical).
For the P6 family processors, the MOV CR0, REG instruction is serializing, so the
jump operation is not required. However, for backwards compatibility, the JMP
instruction should still be included.
19.31 STACK
OPERATIONS
This section identifies the differences in the stack mechanism for the various IA-32
processors.
processors.
19.31.1 Selector Pushes and Pops
When pushing a segment selector onto the stack, the Pentium 4, Intel Xeon, P6
family, and Intel486 processors decrement the ESP register by the operand size and
then write 2 bytes. If the operand size is 32-bits, the upper two bytes of the write are
not modified. The Pentium processor decrements the ESP register by the operand
size and determines the size of the write by the operand size. If the operand size is
32-bits, the upper two bytes are written as 0s.
When popping a segment selector from the stack, the Pentium 4, Intel Xeon, P6
family, and Intel486 processors read 2 bytes and increment the ESP register by the
operand size of the instruction. The Pentium processor determines the size of the
read from the operand size and increments the ESP register by the operand size.
It is possible to align a 32-bit selector push or pop such that the operation generates
an exception on a Pentium processor and not on an Pentium 4, Intel Xeon, P6 family,
or Intel486 processor. This could occur if the third and/or fourth byte of the operation
lies beyond the limit of the segment or if the third and/or fourth byte of the operation
is locate on a non-present or inaccessible page.
For a POP-to-memory instruction that meets the following conditions:
family, and Intel486 processors decrement the ESP register by the operand size and
then write 2 bytes. If the operand size is 32-bits, the upper two bytes of the write are
not modified. The Pentium processor decrements the ESP register by the operand
size and determines the size of the write by the operand size. If the operand size is
32-bits, the upper two bytes are written as 0s.
When popping a segment selector from the stack, the Pentium 4, Intel Xeon, P6
family, and Intel486 processors read 2 bytes and increment the ESP register by the
operand size of the instruction. The Pentium processor determines the size of the
read from the operand size and increments the ESP register by the operand size.
It is possible to align a 32-bit selector push or pop such that the operation generates
an exception on a Pentium processor and not on an Pentium 4, Intel Xeon, P6 family,
or Intel486 processor. This could occur if the third and/or fourth byte of the operation
lies beyond the limit of the segment or if the third and/or fourth byte of the operation
is locate on a non-present or inaccessible page.
For a POP-to-memory instruction that meets the following conditions:
•
The stack segment size is 16-bit.
•
Any 32-bit addressing form with the SIB byte specifying ESP as the base register.