Intel 253668-032US User Manual
2-30 Vol. 3
SYSTEM ARCHITECTURE OVERVIEW
The LMSW (load machine status word) and SMSW (store machine status word)
instructions operate on bits 0 through 15 of control register CR0. These instructions
are provided for compatibility with the 16-bit Intel 286 processor. Programs written
to run on 32-bit IA-32 processors should not use these instructions. Instead, they
should access the control register CR0 using the MOV instruction.
The
instructions operate on bits 0 through 15 of control register CR0. These instructions
are provided for compatibility with the 16-bit Intel 286 processor. Programs written
to run on 32-bit IA-32 processors should not use these instructions. Instead, they
should access the control register CR0 using the MOV instruction.
The
CLTS (clear TS flag in CR0) instruction is provided for use in handling
a
device-not-available exception (#NM) that occurs when the processor attempts to
execute a floating-point instruction when the TS flag is set. This instruction allows
the TS flag to be cleared after the x87 FPU context has been saved, preventing
further #NM exceptions. See Section 2.5, “Control Registers,” for more information
on the TS flag.
The control registers (CR0, CR1, CR2, CR3, CR4, and CR8) are loaded using the MOV
instruction. The instruction loads a control register from a general-purpose register
or stores the content of a control register in a general-purpose register.
execute a floating-point instruction when the TS flag is set. This instruction allows
the TS flag to be cleared after the x87 FPU context has been saved, preventing
further #NM exceptions. See Section 2.5, “Control Registers,” for more information
on the TS flag.
The control registers (CR0, CR1, CR2, CR3, CR4, and CR8) are loaded using the MOV
instruction. The instruction loads a control register from a general-purpose register
or stores the content of a control register in a general-purpose register.
2.7.2
Verifying of Access Privileges
The processor provides several instructions for examining segment selectors
and segment descriptors to determine if access to their associated segments
is allowed. These instructions duplicate some of the automatic access rights
and type checking done by the processor, thus allowing operating-system or
executive software to prevent exceptions from being generated.
The ARPL (adjust RPL) instruction adjusts the RPL (requestor privilege level)
The ARPL (adjust RPL) instruction adjusts the RPL (requestor privilege level)
of a segment selector to match that of the program or procedure that
supplied the segment selector. See Section 5.10.4, “Checking Caller Access
Privileges (ARPL Instruction),” for a detailed explanation of the function and
use of this instruction. Note that ARPL is not supported in 64-bit mode.
The
LAR (load access rights) instruction verifies the accessibility of a speci-
fied segment and loads access rights information from the segment’s
segment descriptor into a general-purpose register. Software can then
examine the access rights to determine if the segment type is compatible
with its intended use. See Section 5.10.1, “Checking Access Rights (LAR
Instruction),” for a detailed explanation of the function and use of this
instruction.
The
LSL (load segment limit) instruction verifies the accessibility of a speci-
fied segment and loads the segment limit from the segment’s segment
descriptor into a general-purpose register. Software can then compare the
segment limit with an offset into the segment to determine whether the
offset lies within the segment. See Section 5.10.3, “Checking That the
Pointer Offset Is Within Limits (LSL Instruction),” for a detailed explanation
of the function and use of this instruction.
The VERR (verify for reading) and VERW (verify for writing) instructions
The VERR (verify for reading) and VERW (verify for writing) instructions
verify if a selected segment is readable or writable, respectively, at a given