Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Data Sheet

Datasheet

143

B/D/F/Type:

0/0/0/PXPEPBAR

Address Offset: 60–63h

Default Value:

02000002h

Access:

RO, RWO 

Size:

32 bits

This register provides the first part of a Link Entry which declares an internal link to 

another Root Complex Element.

B/D/F/Type:

0/0/0/PXPEPBAR

Address Offset: 68–6Fh

Default Value:

0000000000008000h

Access:

RO 

Size:

64 bits

This register provides the second part of a Link Entry which declares an internal link to 

another Root Complex Element.

31:24

RO

02h

Target Port Number (TPN): Specifies the port number associated with the 
element targeted by this link entry (PCI Express). The target port number is with 
respect to the component that contains this element as specified by the target 
component ID.

23:16

RWO

00h

Target Component ID (TCID): Identifies the physical or logical component 
that is targeted by this link entry. A value of 0 is reserved. Component IDs start 
at 1. This value is a mirror of the value in the Component ID field of all elements 
in this component.
BIOS Requirement: Must be initialized according to guidelines in the PCI 
Express* Isochronous/Virtual Channel Support Hardware Programming 
Specification (HPS).

15:2

RO

0000h

Reserved

1

RO

1b

Link Type (LTYP): Indicates that the link points to configuration space of the 
integrated device which controls the root port for PCI Express.
The link address specifies the configuration address (segment, bus, device, 
function) of the target root port.

0

RWO

0b

Link Valid (LV): 
0 = Link Entry is not valid and will be ignored.
1 = Link Entry specifies a valid link.

63:28

RO

0000000

00h

Reserved 

27:20

RO

00h

19:15

RO

00001b Device Number (DEVN): Target for this link is PCI Express port (Device1).

14:12

RO

000b

11:0

RO

000h

Reserved