Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Data Sheet

156

Datasheet

B/D/F/Type:

0/1/0/PCI

Address Offset: 1Ch

Default Value:

F0h

Access:

RO, RW 

Size:

8 bits

This register controls the processor to PCI Express I/O access routing based on the 

following formula: 

IO_BASE ≤ address ≤ IO_LIMIT

Only upper 4 bits are programmable. For the purpose of address decode address bits 

A[11:0] are treated as 0. Thus the bottom of the defined I/O address range will be 

aligned to a 4 KB boundary.

B/D/F/Type:

0/1/0/PCI

Address Offset: 1Dh

Default Value:

00h

Access:

RW, RO 

Size:

8 bits

This register controls the processor to PCI Express I/O access routing based on the 

following formula: 

IO_BASE ≤ address ≤ IO_LIMIT 

Only upper 4 bits are programmable. For the purpose of address decode, address bits 

A[11:0] are assumed to be FFFh. Thus, the top of the defined I/O address range will be 

at the top of a 4 KB aligned address block.

7:4

RW

Fh

I/O Address Base (IOBASE): Corresponds to A[15:12] of the I/O addresses 
passed by bridge 1 to PCI Express. 

3:0

RO

0h

Reserved 

7:4

RW

0h

I/O Address Limit (IOLIMIT): Corresponds to A[15:12] of the I/O address 
limit of device #1. Devices between this upper limit and IOBASE1 will be passed 
to the PCI Express hierarchy associated with this device. 

3:0

RO

0h

Reserved