Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Data Sheet

158

Datasheet

B/D/F/Type:

0/1/0/PCI

Address Offset: 20–21h

Default Value:

FFF0h

Access:

RW, RO 

Size:

16 bits

This register controls the processor to PCI Express non-prefetchable memory access 

routing based on the following formula:

MEMORY_BASE ≤ address ≤ MEMORY_LIMIT 

The upper 12 bits of the register are read/write and correspond to the upper 12 

address bits A[31:20] of the 32 bit address. The bottom 4 bits of this register are read-

only and return zeroes when read. This register must be initialized by the configuration 

software. For the purpose of address decode, address bits A[19:0] are assumed to be 

0. Thus, the bottom of the defined memory address range will be aligned to a 1 MB 

boundary.

15:4

RW

FFFh

Memory Address Base (MBASE): This field corresponds to A[31:20] of the 
lower limit of the memory range that will be passed to PCI Express. 

3:0

RO

0h

Reserved