Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Data Sheet

Datasheet

159

B/D/F/Type:

0/1/0/PCI

Address Offset: 22–23h

Default Value:

0000h

Access:

RW, RO 

Size:

16 bits

This register controls the processor to PCI Express non-prefetchable memory access 

routing based on the following formula:

MEMORY_BASE ≤ address ≤ MEMORY_LIMIT 

The upper 12 bits of the register are read/write and correspond to the upper 12 

address bits A[31:20] of the 32 bit address. The bottom 4 bits of this register are read-

only and return zeroes when read. This register must be initialized by the configuration 

software. For the purpose of address decode address bits A[19:0] are assumed to be 

FFFFFh. Thus, the top of the defined memory address range will be at the top of a 1 MB 

aligned memory block. 

Memory range covered by MBASE and MLIMIT registers are used to map non-

prefetchable PCI Express address ranges (typically where control/status memory-

mapped I/O data structures of the controller will reside) and PMBASE and PMLIMIT are 

used to map prefetchable address ranges (typically device local memory). This 

segregation allows application of USWC space attribute to be performed in a true plug-

and-play manner to the prefetchable address range for improved processor- PCI 

Express memory access performance.

Configuration software is responsible for programming all address range registers 

(prefetchable, non-prefetchable) with the values that provide exclusive address ranges 

(i.e., prevent overlap with each other and/or with the ranges covered with the main 

memory). There is no provision in the MCH hardware to enforce prevention of overlap 

and operations of the system in the case of overlap are not ensured.

15:4

RW

000h

Memory Address Limit (MLIMIT): This field corresponds to A[31:20] of the 
upper limit of the address range passed to PCI Express. 

3:0

RO

0h

Reserved