Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Data Sheet
Product codes
P4X-UPE3210-316-6M1333
Host-Primary PCI Express* Bridge Registers (D1:F0)
174
Datasheet
6.38
LCAP—Link Capabilities
B/D/F/Type:
0/1/0/PCI
Address Offset: AC–AFh
Default Value:
02214D01h
Access:
RO, RWO
Size:
32 bits
This register indicates PCI Express device specific capabilities.
Bit
Access
Default
Value
Description
31:24
RO
02h
Port Number (PN): This field indicates the PCI Express port number for the
given PCI Express link. Matches the value in Element Self Description[31:24].
given PCI Express link. Matches the value in Element Self Description[31:24].
23:22
RO
000b
Reserved
21
RO
1b
Link Bandwidth Notification Capability: A value of 1b indicates support for
the Link Bandwidth Notification status and interrupt mechanisms. This capability
is required for all Root Ports and Switch downstream ports supporting Links
wider than x1 and/or multiple Link speeds.
This field is not applicable and is reserved for Endpoint devices, PCI Express to
PCI/PCI-X bridges, and Upstream Ports of Switches.
Devices that do not implement the Link Bandwidth Notification capability must
hardwire this bit to 0b.
the Link Bandwidth Notification status and interrupt mechanisms. This capability
is required for all Root Ports and Switch downstream ports supporting Links
wider than x1 and/or multiple Link speeds.
This field is not applicable and is reserved for Endpoint devices, PCI Express to
PCI/PCI-X bridges, and Upstream Ports of Switches.
Devices that do not implement the Link Bandwidth Notification capability must
hardwire this bit to 0b.
20
RO
0b
Data Link Layer Link Active Reporting Capable (DLLLARC): For a
Downstream Port, this bit must be set to 1b if the component supports the
optional capability of reporting the DL_Active state of the Data Link Control and
Management State Machine.
For Upstream Ports and components that do not support this optional capability,
this bit must be hardwired to 0b.
Downstream Port, this bit must be set to 1b if the component supports the
optional capability of reporting the DL_Active state of the Data Link Control and
Management State Machine.
For Upstream Ports and components that do not support this optional capability,
this bit must be hardwired to 0b.
19
RO
0b
Surprise Down Error Reporting Capable (SDERC): For a Downstream Port,
this bit must be set to 1b if the component supports the optional capability of
detecting and reporting a Surprise Down error condition.
For Upstream Ports and components that do not support this optional capability,
this bit must be hardwired to 0b.
this bit must be set to 1b if the component supports the optional capability of
detecting and reporting a Surprise Down error condition.
For Upstream Ports and components that do not support this optional capability,
this bit must be hardwired to 0b.
18
RO
0b
Clock Power Management (CPM): A value of 1b in this bit indicates that the
component tolerates the removal of any reference clock(s) when the link is in
the L1 and L2/3 Ready link states. A value of 0b indicates the component does
not have this capability and that reference clock(s) must not be removed in
these link states.
This capability is applicable only in form factors that support "clock request"
(CLKREQ#) capability.
For a multi-function device, each function indicates its capability independently.
Power Management configuration software must only permit reference clock
removal if all functions of the multifunction device indicate a 1b in this bit.
component tolerates the removal of any reference clock(s) when the link is in
the L1 and L2/3 Ready link states. A value of 0b indicates the component does
not have this capability and that reference clock(s) must not be removed in
these link states.
This capability is applicable only in form factors that support "clock request"
(CLKREQ#) capability.
For a multi-function device, each function indicates its capability independently.
Power Management configuration software must only permit reference clock
removal if all functions of the multifunction device indicate a 1b in this bit.
17:15
RWO
010b
L1 Exit Latency (L1ELAT): Indicates the length of time this Port requires to
complete the transition from L1 to L0. The value 010 b indicates the range of 2
us to less than 4 us.
Both bytes of this register that contain a portion of this field must be written
simultaneously in order to prevent an intermediate (and undesired) value from
ever existing.
complete the transition from L1 to L0. The value 010 b indicates the range of 2
us to less than 4 us.
Both bytes of this register that contain a portion of this field must be written
simultaneously in order to prevent an intermediate (and undesired) value from
ever existing.