Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Data Sheet
Product codes
P4X-UPE3210-316-6M1333
Datasheet
203
Intel Manageability Engine Subsystem PCI (D3:F0,F3)
7.1.24
HIDM—HECI Interrupt Delivery Mode
B/D/F/Type:
0/3/0/PCI
Address Offset:
A0h
Default Value:
00h
Access:
RW
Size:
8 bits
BIOS Optimal Default
00h
This register is used to select interrupt delivery mechanism for HECI to Host processor
interrupts.
Bit
Access
Default
Value
Description
7:2
RO
0h
Reserved
1:0
RW
00b
HECI Interrupt Delivery Mode (HIDM): These bits control what type of
interrupt the HECI will send when ME FW writes to set the M_IG bit in AUX
space. They are interpreted as follows:
00 = Generate Legacy or MSI interrupt
01 = Generate SCI
10 = Generate SMI
interrupt the HECI will send when ME FW writes to set the M_IG bit in AUX
space. They are interpreted as follows:
00 = Generate Legacy or MSI interrupt
01 = Generate SCI
10 = Generate SMI