Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Data Sheet

Datasheet

205

B/D/F/Type:

0/3/3/KT MM/IO

Address Offset: 0h

Default Value:

00h

Access:

WO 

Size:

8 bits

This implements the KT Transmit Data register. Host access to this address, depends on 

the state of the DLAB bit {KTLCR[7]). It must be 0 to access the KTTHR.

When host wants to transmit data in the non-FIFO mode, it writes to this register. In 

FIFO mode, writes by host to this address cause the data byte to be written by 

hardware to ME memory (THR FIFO).

Reset: Host System Reset or D3->D0 transition. 

B/D/F/Type:

0/3/3/KT MM/IO

Address Offset: 0h

Default Value:

00h

Access:

RW/V 

Size:

8 bits

This register implements the KT DLL register. Host can Read/Write to this register only 

when the DLAB bit (KTLCR[7]) is 1. When this bit is 0, Host accesses the KTTHR or the 

KTRBR depending on Read or Write.

This is the standard Serial Port Divisor Latch register. This register is only for software 

compatibility and does not affect performance of the hardware.

Reset: Host System Reset or D3->D0 transition.

7:0

WO

00h

Transmit Holding Register (THR): Implements the Transmit Data register of 
the Serial Interface. If Host does a write, it writes to the Transmit Holding 
Register.

7:0

RW/V

00h

Divisor Latch LSB (DLL): Implements the DLL register of the Serial Interface.