Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Data Sheet

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Datasheet

See 

 for a list of PCI Express features, and the PCI Express specification for 

further details.

This MCH is part of a PCI Express root complex. This means it connects a host 

processor/memory subsystem to a PCI Express hierarchy. The control registers for this 

functionality are located in Device 1 and Device 6 configuration space and three Root 

Complex Register Blocks (RCRBs). The DMI RCRB contains registers for control of the 

Intel ICH9 attach ports. 

The PCI Express architecture is specified in layers. Compatibility with the PCI 

addressing model (a load-store architecture with a flat address space) is maintained to 

ensure that all existing applications and drivers operate unchanged. The PCI Express 

configuration uses standard mechanisms as defined in the PCI Plug-and-Play 

specification. The initial speed of 1.25 GHz (250 MHz internally) results in 2.5 Gb/s 

each direction, which provides a 250 MB/s communications channel in each direction 

(500 MB/s total) that is close to twice the data rate of classic PCI per lane. The initial 

speed of 2.5 GHz results in 5 Gb/s each direction, which provides a 500 MB/s 

communications channel in each direction (1000 MB/s total).

The upper layer of the PCI Express architecture is the Transaction Layer. The 

Transaction Layer’s primary responsibility is the assembly and disassembly of 

Transaction Layer Packets (TLPs). TLPs are used to communicate transactions, such as 

read and write, as well as certain types of events. The Transaction Layer also manages 

flow control of TLPs.

The middle layer in the PCI Express stack, the Data Link Layer, serves as an 

intermediate stage between the Transaction Layer and the Physical Layer. 

Responsibilities of Data Link Layer include link management, error detection, and error 

correction.

The Physical Layer includes all circuitry for interface operation, including driver and 

input buffers, parallel-to-serial and serial-to-parallel conversion, PLL(s), and impedance 

matching circuitry.