Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Data Sheet

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Datasheet

Power Management Feature List:

• ACPI 1.0b support
• ACPI S0, S1, S5, C0, C1, and C2 states 
• Enhanced power management state transitions for increasing time processor 

spends in low power states

• PCI Express Link States: L0, L0s, L2/L3 Ready, L3

The MCH has a total of 3 PLLs providing many times that many internal clocks. The 

PLLs are:

• Host PLL – Generates the main core clocks in the host clock domain. Can also be 

used to generate memory core clocks. Uses the Host clock (H_CLKIN) as a 

reference.

• Memory I/O PLL - Optionally generates low jitter clocks for memory I/O interface, 

as opposed to from Host PLL. Uses the Host FSB differential clock (HPL_CLKINP/

HPL_CLKINN) as a reference. Low jitter clock source from memory I/O PLL is 

required for DDR667 and higher frequencies. 

• PCI Express PLL – Generates all PCI Express related clocks, including the Direct 

Media that connect to the ICH. This PLL uses the 100 MHz clock (EXP_CLKNP/

EXP2_CLKNP) as a reference.

CK505 is the clocking chip required for the platform.