Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Data Sheet

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Datasheet

TSEG is optionally 1 MB, 2 MB, or 8 MB in size. TSEG is below stolen memory, which is 

at the top of Low Usable physical memory (TOLUD). SMM-mode processor accesses to 

enabled TSEG access the physical DRAM at the same address. Non-processor 

originated accesses are not allowed to SMM space. PCI Express, and DMI originated 

cycles to enabled SMM space are handled as invalid cycle type with reads and writes to 

location 0 and byte enables turned off for writes. When the extended SMRAM space is 

enabled, processor accesses to the TSEG range without SMM attribute or without WB 

attribute are also forwarded to memory as invalid accesses (see table 8). Non-SMM-

mode Write Back cycles that target TSEG space are completed to DRAM for cache 

coherency. When SMM is enabled the maximum amount of memory available to the 

system is equal to the amount of physical DRAM minus the value in the TSEG register 

which is fixed at 1 MB, 2 MB, or 8 MB. 

Voids of physical addresses that are not accessible as general system memory and 

reside within system memory address range (< TOLUD) are created for SMM-mode, 

and stolen memory. It is the responsibility of BIOS to properly initialize these 

regions. The following table details the location and attributes of the regions. 

Enabling/Disabling these ranges are described in the MCH Control Register Device 0 

(GCC). 

0000_0000h – 03CF_FFFFh

R/W

Available System Memory 61 MB

03D0_0000h – 03DF_FFFFh

SMM Mode Only - 

processor Reads 

TSEG Address Range & Pre-allocated 
memory