Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Data Sheet

Datasheet

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This address range, from the top of low usable DRAM (TOLUD) to 4 GB is normally 

mapped to the DMI Interface.

Device 0 exceptions are:

• Addresses decoded to the egress port registers (PXPEPBAR)
• Addresses decoded to the memory mapped range for internal MCH registers 

(MCHBAR)

• Addresses decoded to the flat memory-mapped address spaced to access device 

configuration registers (PCIEXBAR)

• Addresses decoded to the registers associated with the Direct Media Interface 

(DMI) register memory range. (DMIBAR)

With PCI Express port, there are two exceptions to this rule. 

• Addresses decoded to the PCI Express Memory Window defined by the MBASE1, 

MLIMIT1, registers are mapped to PCI Express.

• Addresses decoded to the PCI Express prefetchable Memory Window defined by the 

PMBASE1, PMLIMIT1, registers are mapped to PCI Express.

In an Intel ME configuration, there are exceptions to this rule:

1. Addresses decoded to the ME Keyboard and Text MMIO range (EPKTBAR)
2. Addresses decoded to the ME HECI MMIO range (EPHECIBAR) 
3. Addresses decoded to the ME HECI2 MMIO range (EPHECI2BAR) 

Some of the MMIO Bars may be mapped to this range or to the range above TOUUD.

There are sub-ranges within the PCI Memory address range defined as APIC 

Configuration Space, FSB Interrupt Space, and High BIOS Address Range. The 

exceptions listed above for the PCI Express ports MUST NOT overlap with these