Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Data Sheet
Product codes
P4X-UPE3210-316-6M1333
Datasheet
81
DRAM Controller Registers (D0:F0)
5.1.20
PAM3—Programmable Attribute Map 3
B/D/F/Type:
0/0/0/PCI
Address Offset: 93h
Default Value:
00h
Access:
RO, RW/L
Size:
8 bits
This register controls the read, write, and shadowing attributes of the BIOS areas from
0D0000h – 0D7FFFh.
Bit
Access
Default
Value
Description
7:6
RO
00b
Reserved
5:4
RW/L
00b
0D4000h–0D7FFFh Attribute (HIENABLE): This field controls the steering of
read and write cycles that address the BIOS area from 0D4000h to 0D7FFFh.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to
read and write cycles that address the BIOS area from 0D4000h to 0D7FFFh.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to
DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
This register is locked by Intel TXT.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
This register is locked by Intel TXT.
3:2
RO
00b
Reserved
1:0
RW/L
00b
0D0000h–0D3FFFh Attribute (LOENABLE): This field controls the steering
of read and write cycles that address the BIOS area from 0D0000h to 0D3FFFh.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to
of read and write cycles that address the BIOS area from 0D0000h to 0D3FFFh.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to
DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
This register is locked by Intel TXT.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
This register is locked by Intel TXT.