Intel Xeon 7130N LF80550KF0878M Data Sheet

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BNR#

I/O

BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is unable to accept 
new bus transactions. During a bus stall, the current bus owner cannot issue any new transactions.

Since multiple agents might need to request a bus stall at the same time, BNR# is a wire-OR signal 
which must connect the appropriate pins of all processor system bus agents. In order to avoid 
wire-OR glitches associated with simultaneous edge transitions driven by multiple drivers, BNR# is 
activated on specific clock edges and sampled on specific clock edges.

BOOT_
SELECT

I

The BOOT_SELECT input informs the processor whether the platform supports the Dual-Core 
Intel Xeon processor 7000 series. Incompatible platform designs will have this input connected to 
V

SS

. Thus, this pin is essentially an electrical key to prevent the Dual-Core Intel Xeon processor 

7000 series from running in a system that is not designed for it. For platforms that are designed to 
support the Dual-Core Intel Xeon processor 7000 series, this pin should be changed to a 
no-connect.

BPM[5:0]#

I/O

BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs 
from the processor which indicate the status of breakpoints and programmable counters used for 
monitoring processor performance. BPM[5:0]# should connect the appropriate pins of all Dual-Core 
Intel Xeon processor 7000 series FSB agents.

BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY# is a processor output 
used by debug tools to determine processor debug readiness.

BPM5# provides PREQ# (Probe Request) functionality for the TAP port. PREQ# is used by debug 
tools to request debug operation of the processors.

BPM[5:4]# must be bussed to all bus agents. Please refer to the appropriate platform design guide 
for more detailed information. 

BPRI#

I

BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor FSB. It must 
connect the appropriate pins of all processor FSB agents. Observing BPRI# active (as asserted by 
the priority agent) causes all other agents to stop issuing new requests, unless such requests are 
part of an ongoing locked operation. The priority agent keeps BPRI# asserted until its requests are 
issued, then releases the bus by deasserting BPRI#.

BR[3:0]#

I/O

BR[3:0]# (Bus Request) drive the BREQ[3:0]# signals in the system. The BREQ[3:0]# signals are 
interconnected in a rotating manner to individual processor pins. The tables below give the rotating 
interconnect between the processor and bus signals for 3-load configurations.

During power-on configuration, the central agent must assert the BREQ0# bus signal. All symmetric 
agents sample their BR[3:0]# pins on the active-to-inactive transition of RESET#. The pin which the 
agent samples asserted determines its agent ID.

BSEL[1:0]

O

These output signals are used to select the FSB frequency. The frequency is determined by the 
processor(s), chipset, and frequency synthesizer capabilities. All FSB agents must operate at the 
same frequency. Individual processors will only operate at their specified FSB frequency. See the 
appropriate platform design guide for implementation examples.

 for output values. Refer to the appropriate platform design guide for termination 

recommendations.

COMP0

I

COMP0 must be terminated to V

SS

 on the baseboard using precision resistors. This input configures 

the AGTL+ drivers of the processor. Refer to the appropriate platform design guide for 
implementation details. 

BREQ0#

BR0#

BR1#

BREQ1#

BR1#

BR0#

BREQ2#

BR2#

BR3#

BREQ3#

BR3#

BR2#