Intel Xeon 7130N LF80550KF0878M Data Sheet

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D[63:0]#

I/O

D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor 
FSB agents, and must connect the appropriate pins on all such agents. The data driver asserts 
DRDY# to indicate a valid data transfer.

D[63:0]# are quad-pumped signals, and will thus be driven four times in a common clock period. 
D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 
data signals correspond to a pair of one DSTBP# and one DSTBN#. The following table shows the 
grouping of data signals to strobes and DBI#.

Furthermore, the DBI# pins determine the polarity of the data signals. Each group of 16 data signals 
corresponds to one DBI# signal. When the DBI# signal is active, the corresponding data group is 
inverted and therefore sampled active high. 

DBI[3:0]#

I/O

DBI[3:0]# are source synchronous and indicate the polarity of the D[63:0]# signals. The DBI[3:0]# 
signals are activated when the data on the data bus is inverted. If more than half the data bits, within 
a 16-bit group, would have been asserted electronically low, the bus agent may invert the data bus 
signals for that particular sub-phase for that 16-bit group.

DBSY#

I/O

DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the processor FSB 
to indicate that the data bus is in use. The data bus is released after DBSY# is deasserted. This 
signal must connect the appropriate pins on all processor FSB agents.

DEFER#

I

DEFER# is asserted by an agent to indicate that a transaction cannot be guaranteed in-order 
completion. Assertion of DEFER# is normally the responsibility of the addressed memory or I/O 
agent. This signal must connect the appropriate pins of all processor FSB agents.

DP[3:0]#

I/O

DP[3:0]# (Data Parity) provide optional parity protection for the data bus. They are driven by the 
agent responsible for driving D[63:0]#, and, if parity is implemented, must connect the appropriate 
pins of all bus agents which use them.

DRDY#

I/O

DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on 
the data bus. In a multi-common clock data transfer, DRDY# may be deasserted to insert idle clocks. 
This signal must connect the appropriate pins of all processor FSB agents.

DSTBN[3:0]#

I/O

Data strobe used to latch in D[63:0]# and DBI[3:0]#.

DSTBP[3:0]#

I/O

Data strobe used to latch in D[63:0]# and DBI[3:0]#.

FERR#/PBE#

O

FERR#/PBE# (floating-point error/pending break event) is a multiplexed signal and its meaning is 
qualified by STPCLK#. When STPCLK# is not asserted, FERR#/PBE# indicates a floating-point 
error and will be asserted when the processor detects an unmasked floating-point error. When 
STPCLK# is not asserted, FERR#/PBE# is similar to the ERROR# signal on the Intel

®

387 

coprocessor, and is included for compatibility with systems using MS-DOS*-type floating-point error 
reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the processor 
has a pending break event waiting for service. The assertion of FERR#/PBE# indicates that the 
processor should be returned to the Normal state. For additional information on the pending break 
event functionality, including the identification of support of the feature and enable/disable 
information, refer to Vol 3 of the IA-32 Intel

 Architecture Software Developer’s Manual and the 

 Processor Identification and the CPUID Instruction application note.

FORCEPR#

I

This input can be used to force activation of the Thermal Control Circuit.

GTLREF[3:0]

I

GTLREF determines the signal reference level for AGTL+ input pins. GTLREF is used by the AGTL+ 
receivers to determine if a signal is an electrical 0 or an electrical 1. 

DBI0#

D[15:0]#

DBI1#

D[31:16]#

DBI2#

D[47:32]#

DBI3#

D[63:48]#