Intel 1005M AW8063801121200 User Manual
Product codes
AW8063801121200
Datasheet, Volume 1
47
Technologies
AES-NI consists of six Intel SSE instructions. Four instructions, namely AESENC,
AESENCLAST, AESDEC, and AESDELAST facilitate high performance AES encryption and
decryption. The other two, AESIMC and AESKEYGENASSIST, support the AES key
expansion procedure. Together, these instructions provide a full hardware for support
AES, offering security, high performance, and a great deal of flexibility.
AESENCLAST, AESDEC, and AESDELAST facilitate high performance AES encryption and
decryption. The other two, AESIMC and AESKEYGENASSIST, support the AES key
expansion procedure. Together, these instructions provide a full hardware for support
AES, offering security, high performance, and a great deal of flexibility.
3.6.2
PCLMULQDQ Instruction
The processor supports the carry-less multiplication instruction, PCLMULQDQ.
PCLMULQDQ is a Single Instruction Multiple Data (SIMD) instruction that computes the
128-bit carry-less multiplication of two, 64-bit operands without generating and
propagating carries. Carry-less multiplication is an essential processing component of
several cryptographic systems and standards. Hence, accelerating carry-less
multiplication can significantly contribute to achieving high speed secure computing
and communication.
PCLMULQDQ is a Single Instruction Multiple Data (SIMD) instruction that computes the
128-bit carry-less multiplication of two, 64-bit operands without generating and
propagating carries. Carry-less multiplication is an essential processing component of
several cryptographic systems and standards. Hence, accelerating carry-less
multiplication can significantly contribute to achieving high speed secure computing
and communication.
3.6.3
RDRAND Instruction
The processor introduces a software visible random number generation mechanism
supported by a high quality entropy source. This capability will be made available to
programmers through the new RDRAND instruction. The resultant random number
generation capability is designed to comply with existing industry standards in this
regard (ANSI X9.82 and NIST SP 800-90).
supported by a high quality entropy source. This capability will be made available to
programmers through the new RDRAND instruction. The resultant random number
generation capability is designed to comply with existing industry standards in this
regard (ANSI X9.82 and NIST SP 800-90).
Some possible usages of the new RDRAND instruction include cryptographic key
generation as used in a variety of applications including communication, digital
signatures, secure storage, and so on.
generation as used in a variety of applications including communication, digital
signatures, secure storage, and so on.
3.7
Intel
®
64 Architecture x2APIC
The Intel x2APIC architecture extends the xAPIC architecture that provides key
mechanism for interrupt delivery. This extension is intended primarily to increase
processor addressability.
mechanism for interrupt delivery. This extension is intended primarily to increase
processor addressability.
Specifically, x2APIC:
• Retains all key elements of compatibility to the xAPIC architecture:
— delivery modes
— interrupt and processor priorities
— interrupt sources
— interrupt destination types
— interrupt and processor priorities
— interrupt sources
— interrupt destination types
• Provides extensions to scale processor addressability for both the logical and
physical destination modes
• Adds new features to enhance performance of interrupt delivery
• Reduces complexity of logical destination mode interrupt delivery on link based
• Reduces complexity of logical destination mode interrupt delivery on link based
architectures
The key enhancements provided by the x2APIC architecture over xAPIC are the
following:
following:
• Support for two modes of operation to provide backward compatibility and
extensibility for future platform innovations: