Intel 1005M AW8063801121200 User Manual

48

Datasheet, Volume 1

— In xAPIC compatibility mode, APIC registers are accessed through memory 

mapped interface to a 4

 

KB page, identical to the xAPIC architecture.

— In x2APIC mode, APIC registers are accessed through Model Specific Register 

(MSR) interfaces. In this mode, the x2APIC architecture provides significantly 

increased processor addressability and some enhancements on interrupt 

delivery.

• Increased range of processor addressability in x2APIC mode:

— Physical xAPIC ID field increases from 8 bits to 32 bits, allowing for interrupt 

processor addressability up to 4

  GB-1 processors in physical destination mode. 

A processor implementation of x2APIC architecture can support fewer than 

32

 

bits in a software transparent fashion.

— Logical xAPIC ID field increases from 8 bits to 32 bits. The 32-bit logical x2APIC 

ID is partitioned into two sub-fields – a 16-bit cluster ID and a 16-bit logical ID 

within the cluster. Consequently, ((2^20) -16) processors can be addressed in 

logical destination mode. Processor implementations can support fewer than 

16

 

bits in the cluster ID sub-field and logical ID sub-field in a software agnostic 

fashion.

• More efficient MSR interface to access APIC registers.

— To enhance inter-processor and self directed interrupt delivery as well as the 

ability to virtualize the local APIC, the APIC register set can be accessed only 

through MSR based interfaces in the x2APIC mode. The Memory Mapped IO 

(MMIO) interface used by xAPIC is not supported in the x2APIC mode.

• The semantics for accessing APIC registers have been revised to simplify the 

programming of frequently-used APIC registers by system software. Specifically 
the software semantics for using the Interrupt Command Register (ICR) and End Of 
Interrupt (EOI) registers have been modified to allow for more efficient delivery 
and dispatching of interrupts.

The x2APIC extensions are made available to system software by enabling the local 
x2APIC unit in the “x2APIC” mode. To benefit from x2APIC capabilities, a new operating 
system and a new BIOS are both needed, with special support for the x2APIC mode.

The x2APIC architecture provides backward compatibility to the xAPIC architecture and 
forward extendibility for future Intel platform innovations.

Intel x2APIC technology may not be available on all SKUs.

For more information, refer to the Intel 64 Architecture x2APIC specification at 

http://www.intel.com/products/processor/manuals/

The processor introduces a new mechanism that provides next level of system 
protection by blocking malicious software attacks from user mode code when the 
system is running in the highest privilege level.

This technology helps to protect from virus attacks and unwanted code to harm the 
system.

For more information, please refer to the Intel

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